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📄 altsyncram_vj31.tdf

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			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 48,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 48,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a49 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 49,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 49,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a50 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 50,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 50,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a51 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 51,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 51,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a52 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 52,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 52,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a53 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 53,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 53,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a54 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 54,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 54,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a55 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 55,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 55,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a56 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 56,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 56,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a57 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 57,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 57,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a58 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 58,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 58,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a59 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 59,
			PORT_A_LAST_ADDRESS = 2,
			PORT_A_LOGICAL_RAM_DEPTH = 3,
			PORT_A_LOGICAL_RAM_WIDTH = 257,
			PORT_B_ADDRESS_CLOCK = "clock0",
			PORT_B_ADDRESS_WIDTH = 2,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_OUT_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 59,
			PORT_B_LAST_ADDRESS = 2,
			PORT_B_LOGICAL_RAM_DEPTH = 3,
			PORT_B_LOGICAL_RAM_WIDTH = 257,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock0",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block5a60 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			DONT_POWER_OPTIMIZE = "ON",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 2,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 60,
			PORT_A_L
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