📄 parallel_add0.vhd
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-- megafunction wizard: %PARALLEL_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: parallel_add
-- ============================================================
-- File Name: parallel_add0.vhd
-- Megafunction Name(s):
-- parallel_add
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 4.2 Build 157 12/07/2004 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related netlist (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--associated documentation or information provided by Altera or a partner
--under Altera's Megafunction Partnership Program may be used only
--to program PLD devices (but not masked PLD devices) from Altera. Any
--other use of such megafunction design, netlist, support information,
--device programming or simulation file, or any other related documentation
--or information is prohibited for any other purpose, including, but not
--limited to modification, reverse engineering, de-compiling, or use with
--any other silicon devices, unless such use is explicitly licensed under
--a separate agreement with Altera or a megafunction partner. Title to the
--intellectual property, including patents, copyrights, trademarks, trade
--secrets, or maskworks, embodied in any such megafunction design, netlist,
--support information, device programming or simulation file, or any other
--related documentation or information provided by Altera or a megafunction
--partner, remains with Altera, the megafunction partner, or their respective
--licensors. No other licenses, including any licenses needed under any third
--party's intellectual property, are provided herein.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY parallel_add0 IS
PORT
(
data15x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data14x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data9x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
clock : IN STD_LOGIC := '0';
data13x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data8x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data12x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data11x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data10x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
);
END parallel_add0;
ARCHITECTURE SYN OF parallel_add0 IS
-- type ALTERA_MF_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (19 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire2 : ALTERA_MF_LOGIC_2D (15 DOWNTO 0, 15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire10 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire11 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire12 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire13 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire14 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire15 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire16 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire17 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT parallel_add
GENERIC (
width : NATURAL;
representation : STRING;
size : NATURAL;
msw_subtract : STRING;
pipeline : NATURAL;
result_alignment : STRING;
widthr : NATURAL;
shift : NATURAL;
lpm_type : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN ALTERA_MF_LOGIC_2D (15 DOWNTO 0, 15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (19 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire17 <= data0x(15 DOWNTO 0);
sub_wire16 <= data1x(15 DOWNTO 0);
sub_wire15 <= data2x(15 DOWNTO 0);
sub_wire14 <= data3x(15 DOWNTO 0);
sub_wire13 <= data4x(15 DOWNTO 0);
sub_wire12 <= data5x(15 DOWNTO 0);
sub_wire11 <= data6x(15 DOWNTO 0);
sub_wire10 <= data7x(15 DOWNTO 0);
sub_wire9 <= data8x(15 DOWNTO 0);
sub_wire8 <= data9x(15 DOWNTO 0);
sub_wire7 <= data10x(15 DOWNTO 0);
sub_wire6 <= data11x(15 DOWNTO 0);
sub_wire5 <= data12x(15 DOWNTO 0);
sub_wire4 <= data13x(15 DOWNTO 0);
sub_wire3 <= data14x(15 DOWNTO 0);
result <= sub_wire0(19 DOWNTO 0);
sub_wire1 <= data15x(15 DOWNTO 0);
sub_wire2(15, 0) <= sub_wire1(0);
sub_wire2(15, 1) <= sub_wire1(1);
sub_wire2(15, 2) <= sub_wire1(2);
sub_wire2(15, 3) <= sub_wire1(3);
sub_wire2(15, 4) <= sub_wire1(4);
sub_wire2(15, 5) <= sub_wire1(5);
sub_wire2(15, 6) <= sub_wire1(6);
sub_wire2(15, 7) <= sub_wire1(7);
sub_wire2(15, 8) <= sub_wire1(8);
sub_wire2(15, 9) <= sub_wire1(9);
sub_wire2(15, 10) <= sub_wire1(10);
sub_wire2(15, 11) <= sub_wire1(11);
sub_wire2(15, 12) <= sub_wire1(12);
sub_wire2(15, 13) <= sub_wire1(13);
sub_wire2(15, 14) <= sub_wire1(14);
sub_wire2(15, 15) <= sub_wire1(15);
sub_wire2(14, 0) <= sub_wire3(0);
sub_wire2(14, 1) <= sub_wire3(1);
sub_wire2(14, 2) <= sub_wire3(2);
sub_wire2(14, 3) <= sub_wire3(3);
sub_wire2(14, 4) <= sub_wire3(4);
sub_wire2(14, 5) <= sub_wire3(5);
sub_wire2(14, 6) <= sub_wire3(6);
sub_wire2(14, 7) <= sub_wire3(7);
sub_wire2(14, 8) <= sub_wire3(8);
sub_wire2(14, 9) <= sub_wire3(9);
sub_wire2(14, 10) <= sub_wire3(10);
sub_wire2(14, 11) <= sub_wire3(11);
sub_wire2(14, 12) <= sub_wire3(12);
sub_wire2(14, 13) <= sub_wire3(13);
sub_wire2(14, 14) <= sub_wire3(14);
sub_wire2(14, 15) <= sub_wire3(15);
sub_wire2(13, 0) <= sub_wire4(0);
sub_wire2(13, 1) <= sub_wire4(1);
sub_wire2(13, 2) <= sub_wire4(2);
sub_wire2(13, 3) <= sub_wire4(3);
sub_wire2(13, 4) <= sub_wire4(4);
sub_wire2(13, 5) <= sub_wire4(5);
sub_wire2(13, 6) <= sub_wire4(6);
sub_wire2(13, 7) <= sub_wire4(7);
sub_wire2(13, 8) <= sub_wire4(8);
sub_wire2(13, 9) <= sub_wire4(9);
sub_wire2(13, 10) <= sub_wire4(10);
sub_wire2(13, 11) <= sub_wire4(11);
sub_wire2(13, 12) <= sub_wire4(12);
sub_wire2(13, 13) <= sub_wire4(13);
sub_wire2(13, 14) <= sub_wire4(14);
sub_wire2(13, 15) <= sub_wire4(15);
sub_wire2(12, 0) <= sub_wire5(0);
sub_wire2(12, 1) <= sub_wire5(1);
sub_wire2(12, 2) <= sub_wire5(2);
sub_wire2(12, 3) <= sub_wire5(3);
sub_wire2(12, 4) <= sub_wire5(4);
sub_wire2(12, 5) <= sub_wire5(5);
sub_wire2(12, 6) <= sub_wire5(6);
sub_wire2(12, 7) <= sub_wire5(7);
sub_wire2(12, 8) <= sub_wire5(8);
sub_wire2(12, 9) <= sub_wire5(9);
sub_wire2(12, 10) <= sub_wire5(10);
sub_wire2(12, 11) <= sub_wire5(11);
sub_wire2(12, 12) <= sub_wire5(12);
sub_wire2(12, 13) <= sub_wire5(13);
sub_wire2(12, 14) <= sub_wire5(14);
sub_wire2(12, 15) <= sub_wire5(15);
sub_wire2(11, 0) <= sub_wire6(0);
sub_wire2(11, 1) <= sub_wire6(1);
sub_wire2(11, 2) <= sub_wire6(2);
sub_wire2(11, 3) <= sub_wire6(3);
sub_wire2(11, 4) <= sub_wire6(4);
sub_wire2(11, 5) <= sub_wire6(5);
sub_wire2(11, 6) <= sub_wire6(6);
sub_wire2(11, 7) <= sub_wire6(7);
sub_wire2(11, 8) <= sub_wire6(8);
sub_wire2(11, 9) <= sub_wire6(9);
sub_wire2(11, 10) <= sub_wire6(10);
sub_wire2(11, 11) <= sub_wire6(11);
sub_wire2(11, 12) <= sub_wire6(12);
sub_wire2(11, 13) <= sub_wire6(13);
sub_wire2(11, 14) <= sub_wire6(14);
sub_wire2(11, 15) <= sub_wire6(15);
sub_wire2(10, 0) <= sub_wire7(0);
sub_wire2(10, 1) <= sub_wire7(1);
sub_wire2(10, 2) <= sub_wire7(2);
sub_wire2(10, 3) <= sub_wire7(3);
sub_wire2(10, 4) <= sub_wire7(4);
sub_wire2(10, 5) <= sub_wire7(5);
sub_wire2(10, 6) <= sub_wire7(6);
sub_wire2(10, 7) <= sub_wire7(7);
sub_wire2(10, 8) <= sub_wire7(8);
sub_wire2(10, 9) <= sub_wire7(9);
sub_wire2(10, 10) <= sub_wire7(10);
sub_wire2(10, 11) <= sub_wire7(11);
sub_wire2(10, 12) <= sub_wire7(12);
sub_wire2(10, 13) <= sub_wire7(13);
sub_wire2(10, 14) <= sub_wire7(14);
sub_wire2(10, 15) <= sub_wire7(15);
sub_wire2(9, 0) <= sub_wire8(0);
sub_wire2(9, 1) <= sub_wire8(1);
sub_wire2(9, 2) <= sub_wire8(2);
sub_wire2(9, 3) <= sub_wire8(3);
sub_wire2(9, 4) <= sub_wire8(4);
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