📄 a8255.map.rpt
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+---------------------------------------------+-------+
; Total logic elements ; 166 ;
; -- Combinational with no register ; 112 ;
; -- Register only ; 40 ;
; -- Combinational with a register ; 14 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 84 ;
; -- 3 input functions ; 27 ;
; -- 2 input functions ; 9 ;
; -- 1 input functions ; 6 ;
; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 166 ;
; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 3 ;
; -- asynchronous clear/load mode ; 54 ;
; ; ;
; Total registers ; 54 ;
; I/O pins ; 81 ;
; Maximum fan-out node ; CLK ;
; Maximum fan-out ; 54 ;
; Total fan-out ; 676 ;
; Average fan-out ; 2.74 ;
+---------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
; |a8255 ; 166 (0) ; 54 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 81 ; 0 ; 112 (0) ; 40 (0) ; 14 (0) ; 0 (0) ; 0 (0) ; |a8255 ;
; |cntl_log:I_cntl_log| ; 35 (35) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 (0) ; |a8255|cntl_log:I_cntl_log ;
; |dout_mux:I_dout_mux| ; 34 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |a8255|dout_mux:I_dout_mux ;
; |portain:I_portain| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |a8255|portain:I_portain ;
; |portaout:I_portaout| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |a8255|portaout:I_portaout ;
; |portbin:I_portbin| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |a8255|portbin:I_portbin ;
; |portbout:I_portbout| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |a8255|portbout:I_portbout ;
; |portcout:I_portcout| ; 65 (65) ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 50 (50) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 (0) ; |a8255|portcout:I_portcout ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 54 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 3 ;
; Number of registers using Asynchronous Clear ; 54 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 39 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; cntl_log:I_cntl_log|ControlRegQ[0] ; 4 ;
; cntl_log:I_cntl_log|ControlRegQ[1] ; 6 ;
; cntl_log:I_cntl_log|ControlRegQ[3] ; 5 ;
; cntl_log:I_cntl_log|ControlRegQ[4] ; 11 ;
; Total number of inverted registers = 4 ; ;
+----------------------------------------+---------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |a8255|cntl_log:I_cntl_log|PortCOutLd[3] ;
; 8:1 ; 4 bits ; 20 LEs ; 16 LEs ; 4 LEs ; No ; |a8255|dout_mux:I_dout_mux|Mux6 ;
; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |a8255|cntl_log:I_cntl_log|PCEN[5] ;
; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |a8255|cntl_log:I_cntl_log|PCEN[7] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Apr 01 21:20:44 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255
Warning: Using design file A8255.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: a8255-structure
Info: Found entity 1: a8255
Info: Elaborating entity "A8255" for the top level hierarchy
Warning: Using design file dout_mux.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: dout_mux-rtl
Info: Found entity 1: dout_mux
Info: Elaborating entity "dout_mux" for hierarchy "dout_mux:I_dout_mux"
Warning (10005): Verilog HDL or VHDL warning at dout_mux.vhd(50): sensitivity list already contains DOUTSelect
Warning: Using design file cntl_log.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: cntl_log-rtl
Info: Found entity 1: cntl_log
Info: Elaborating entity "cntl_log" for hierarchy "cntl_log:I_cntl_log"
Warning: Using design file portaout.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: portaout-rtl
Info: Found entity 1: portaout
Info: Elaborating entity "portaout" for hierarchy "portaout:I_portaout"
Warning: Using design file portain.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: portain-rtl
Info: Found entity 1: portain
Info: Elaborating entity "portain" for hierarchy "portain:I_portain"
Warning: Using design file portbout.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: portbout-rtl
Info: Found entity 1: portbout
Info: Elaborating entity "portbout" for hierarchy "portbout:I_portbout"
Warning: Using design file portbin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: portbin-rtl
Info: Found entity 1: portbin
Info: Elaborating entity "portbin" for hierarchy "portbin:I_portbin"
Warning: Using design file portcout.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: portcout-rtl
Info: Found entity 1: portcout
Info: Elaborating entity "portcout" for hierarchy "portcout:I_portcout"
Info: Registers with preset signals will power-up high
Info: Implemented 247 device resources after synthesis - the final resource count might be different
Info: Implemented 39 input pins
Info: Implemented 42 output pins
Info: Implemented 166 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
Info: Processing ended: Tue Apr 01 21:20:52 2008
Info: Elapsed time: 00:00:09
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