a8255.hier_info

8255并行接口芯片得VHDL描述

|A8255
RESET => portcout:I_portcout.RESET
RESET => portbin:I_portbin.RESET
RESET => portbout:I_portbout.RESET
RESET => portain:I_portain.RESET
RESET => portaout:I_portaout.RESET
RESET => cntl_log:I_cntl_log.RESET
CLK => portcout:I_portcout.CLK
CLK => portbin:I_portbin.CLK
CLK => portbout:I_portbout.CLK
CLK => portain:I_portain.CLK
CLK => portaout:I_portaout.CLK
CLK => cntl_log:I_cntl_log.CLK
nCS => cntl_log:I_cntl_log.nCS
nRD => cntl_log:I_cntl_log.nRD
nWR => cntl_log:I_cntl_log.nWR
A[0] => cntl_log:I_cntl_log.A[0]
A[1] => cntl_log:I_cntl_log.A[1]
DIN[0] => portcout:I_portcout.DIN[0]
DIN[0] => portbout:I_portbout.DIN[0]
DIN[0] => portaout:I_portaout.DIN[0]
DIN[0] => cntl_log:I_cntl_log.DIN[0]
DIN[1] => portcout:I_portcout.DIN[1]
DIN[1] => portbout:I_portbout.DIN[1]
DIN[1] => portaout:I_portaout.DIN[1]
DIN[1] => cntl_log:I_cntl_log.DIN[1]
DIN[2] => portcout:I_portcout.DIN[2]
DIN[2] => portbout:I_portbout.DIN[2]
DIN[2] => portaout:I_portaout.DIN[2]
DIN[2] => cntl_log:I_cntl_log.DIN[2]
DIN[3] => portcout:I_portcout.DIN[3]
DIN[3] => portbout:I_portbout.DIN[3]
DIN[3] => portaout:I_portaout.DIN[3]
DIN[3] => cntl_log:I_cntl_log.DIN[3]
DIN[4] => portcout:I_portcout.DIN[4]
DIN[4] => portbout:I_portbout.DIN[4]
DIN[4] => portaout:I_portaout.DIN[4]
DIN[4] => cntl_log:I_cntl_log.DIN[4]
DIN[5] => portcout:I_portcout.DIN[5]
DIN[5] => portbout:I_portbout.DIN[5]
DIN[5] => portaout:I_portaout.DIN[5]
DIN[5] => cntl_log:I_cntl_log.DIN[5]
DIN[6] => portcout:I_portcout.DIN[6]
DIN[6] => portbout:I_portbout.DIN[6]
DIN[6] => portaout:I_portaout.DIN[6]
DIN[6] => cntl_log:I_cntl_log.DIN[6]
DIN[7] => portcout:I_portcout.DIN[7]
DIN[7] => portbout:I_portbout.DIN[7]
DIN[7] => portaout:I_portaout.DIN[7]
DIN[7] => cntl_log:I_cntl_log.DIN[7]
PAIN[0] => portain:I_portain.PAIN[0]
PAIN[0] => dout_mux:I_dout_mux.PAIN[0]
PAIN[1] => portain:I_portain.PAIN[1]
PAIN[1] => dout_mux:I_dout_mux.PAIN[1]
PAIN[2] => portain:I_portain.PAIN[2]
PAIN[2] => dout_mux:I_dout_mux.PAIN[2]
PAIN[3] => portain:I_portain.PAIN[3]
PAIN[3] => dout_mux:I_dout_mux.PAIN[3]
PAIN[4] => portain:I_portain.PAIN[4]
PAIN[4] => dout_mux:I_dout_mux.PAIN[4]
PAIN[5] => portain:I_portain.PAIN[5]
PAIN[5] => dout_mux:I_dout_mux.PAIN[5]
PAIN[6] => portain:I_portain.PAIN[6]
PAIN[6] => dout_mux:I_dout_mux.PAIN[6]
PAIN[7] => portain:I_portain.PAIN[7]
PAIN[7] => dout_mux:I_dout_mux.PAIN[7]
PBIN[0] => portbin:I_portbin.PBIN[0]
PBIN[0] => dout_mux:I_dout_mux.PBIN[0]
PBIN[1] => portbin:I_portbin.PBIN[1]
PBIN[1] => dout_mux:I_dout_mux.PBIN[1]
PBIN[2] => portbin:I_portbin.PBIN[2]
PBIN[2] => dout_mux:I_dout_mux.PBIN[2]
PBIN[3] => portbin:I_portbin.PBIN[3]
PBIN[3] => dout_mux:I_dout_mux.PBIN[3]
PBIN[4] => portbin:I_portbin.PBIN[4]
PBIN[4] => dout_mux:I_dout_mux.PBIN[4]
PBIN[5] => portbin:I_portbin.PBIN[5]
PBIN[5] => dout_mux:I_dout_mux.PBIN[5]
PBIN[6] => portbin:I_portbin.PBIN[6]
PBIN[6] => dout_mux:I_dout_mux.PBIN[6]
PBIN[7] => portbin:I_portbin.PBIN[7]
PBIN[7] => dout_mux:I_dout_mux.PBIN[7]
PCIN[0] => dout_mux:I_dout_mux.PortCStatus[0]
PCIN[0] => portcout:I_portcout.PCIN[0]
PCIN[0] => cntl_log:I_cntl_log.PCIN[0]
PCIN[1] => dout_mux:I_dout_mux.PortCStatus[1]
PCIN[1] => portcout:I_portcout.PCIN[1]
PCIN[1] => cntl_log:I_cntl_log.PCIN[1]
PCIN[2] => portcout:I_portcout.PCIN[2]
PCIN[2] => portbin:I_portbin.PortBInLd
PCIN[2] => cntl_log:I_cntl_log.PCIN[2]
PCIN[3] => dout_mux:I_dout_mux.PortCStatus[3]
PCIN[3] => portcout:I_portcout.PCIN[3]
PCIN[3] => cntl_log:I_cntl_log.PCIN[3]
PCIN[4] => portcout:I_portcout.PCIN[4]
PCIN[4] => portain:I_portain.PortAInLd
PCIN[4] => cntl_log:I_cntl_log.PCIN[4]
PCIN[5] => dout_mux:I_dout_mux.PortCStatus[5]
PCIN[5] => portcout:I_portcout.PCIN[5]
PCIN[5] => cntl_log:I_cntl_log.PCIN[5]
PCIN[6] => portcout:I_portcout.PCIN[6]
PCIN[6] => cntl_log:I_cntl_log.PCIN[6]
PCIN[7] => dout_mux:I_dout_mux.PortCStatus[7]
PCIN[7] => portcout:I_portcout.PCIN[7]
PCIN[7] => cntl_log:I_cntl_log.PCIN[7]
DOUT[0] <= dout_mux:I_dout_mux.DOUT[0]
DOUT[1] <= dout_mux:I_dout_mux.DOUT[1]
DOUT[2] <= dout_mux:I_dout_mux.DOUT[2]
DOUT[3] <= dout_mux:I_dout_mux.DOUT[3]
DOUT[4] <= dout_mux:I_dout_mux.DOUT[4]
DOUT[5] <= dout_mux:I_dout_mux.DOUT[5]
DOUT[6] <= dout_mux:I_dout_mux.DOUT[6]
DOUT[7] <= dout_mux:I_dout_mux.DOUT[7]
PAOUT[0] <= portaout:I_portaout.PAOUT[0]
PAOUT[1] <= portaout:I_portaout.PAOUT[1]
PAOUT[2] <= portaout:I_portaout.PAOUT[2]
PAOUT[3] <= portaout:I_portaout.PAOUT[3]
PAOUT[4] <= portaout:I_portaout.PAOUT[4]
PAOUT[5] <= portaout:I_portaout.PAOUT[5]
PAOUT[6] <= portaout:I_portaout.PAOUT[6]
PAOUT[7] <= portaout:I_portaout.PAOUT[7]
PAEN <= cntl_log:I_cntl_log.PAEN
PBOUT[0] <= portbout:I_portbout.PBOUT[0]
PBOUT[1] <= portbout:I_portbout.PBOUT[1]
PBOUT[2] <= portbout:I_portbout.PBOUT[2]
PBOUT[3] <= portbout:I_portbout.PBOUT[3]
PBOUT[4] <= portbout:I_portbout.PBOUT[4]
PBOUT[5] <= portbout:I_portbout.PBOUT[5]
PBOUT[6] <= portbout:I_portbout.PBOUT[6]
PBOUT[7] <= portbout:I_portbout.PBOUT[7]
PBEN <= cntl_log:I_cntl_log.PBEN
PCOUT[0] <= portcout:I_portcout.PCOUT[0]
PCOUT[1] <= portcout:I_portcout.PCOUT[1]
PCOUT[2] <= portcout:I_portcout.PCOUT[2]
PCOUT[3] <= portcout:I_portcout.PCOUT[3]
PCOUT[4] <= portcout:I_portcout.PCOUT[4]
PCOUT[5] <= portcout:I_portcout.PCOUT[5]
PCOUT[6] <= portcout:I_portcout.PCOUT[6]
PCOUT[7] <= portcout:I_portcout.PCOUT[7]
PCEN[0] <= cntl_log:I_cntl_log.PCEN[0]
PCEN[1] <= cntl_log:I_cntl_log.PCEN[1]
PCEN[2] <= cntl_log:I_cntl_log.PCEN[2]
PCEN[3] <= cntl_log:I_cntl_log.PCEN[3]
PCEN[4] <= cntl_log:I_cntl_log.PCEN[4]
PCEN[5] <= cntl_log:I_cntl_log.PCEN[5]
PCEN[6] <= cntl_log:I_cntl_log.PCEN[6]
PCEN[7] <= cntl_log:I_cntl_log.PCEN[7]


|A8255|dout_mux:I_dout_mux
DOUTSelect[0] => Mux0.IN4
DOUTSelect[0] => Mux1.IN4
DOUTSelect[0] => Mux2.IN4
DOUTSelect[0] => Mux3.IN4
DOUTSelect[0] => Mux4.IN4
DOUTSelect[0] => Mux5.IN4
DOUTSelect[0] => Mux6.IN4
DOUTSelect[0] => Mux7.IN4
DOUTSelect[1] => Mux0.IN3
DOUTSelect[1] => Mux1.IN3
DOUTSelect[1] => Mux2.IN3
DOUTSelect[1] => Mux3.IN3
DOUTSelect[1] => Mux4.IN3
DOUTSelect[1] => Mux5.IN3
DOUTSelect[1] => Mux6.IN3
DOUTSelect[1] => Mux7.IN3
DOUTSelect[2] => Mux0.IN2
DOUTSelect[2] => Mux1.IN2
DOUTSelect[2] => Mux2.IN2
DOUTSelect[2] => Mux3.IN2
DOUTSelect[2] => Mux4.IN2
DOUTSelect[2] => Mux5.IN2
DOUTSelect[2] => Mux6.IN2
DOUTSelect[2] => Mux7.IN2
ControlReg[0] => Mux7.IN5
ControlReg[1] => Mux6.IN5
ControlReg[2] => Mux5.IN5
ControlReg[3] => Mux4.IN5
ControlReg[4] => Mux3.IN5
ControlReg[5] => Mux2.IN5
ControlReg[6] => Mux1.IN5
ControlReg[7] => Mux0.IN5
PortAInReg[0] => Mux7.IN6
PortAInReg[1] => Mux6.IN6
PortAInReg[2] => Mux5.IN6
PortAInReg[3] => Mux4.IN6
PortAInReg[4] => Mux3.IN6
PortAInReg[5] => Mux2.IN6
PortAInReg[6] => Mux1.IN6
PortAInReg[7] => Mux0.IN6
PAIN[0] => Mux7.IN7
PAIN[1] => Mux6.IN7
PAIN[2] => Mux5.IN7
PAIN[3] => Mux4.IN7
PAIN[4] => Mux3.IN7
PAIN[5] => Mux2.IN7
PAIN[6] => Mux1.IN7
PAIN[7] => Mux0.IN7
PortBInReg[0] => Mux7.IN8
PortBInReg[1] => Mux6.IN8
PortBInReg[2] => Mux5.IN8
PortBInReg[3] => Mux4.IN8
PortBInReg[4] => Mux3.IN8
PortBInReg[5] => Mux2.IN8
PortBInReg[6] => Mux1.IN8
PortBInReg[7] => Mux0.IN8
PBIN[0] => Mux7.IN9
PBIN[1] => Mux6.IN9
PBIN[2] => Mux5.IN9
PBIN[3] => Mux4.IN9
PBIN[4] => Mux3.IN9
PBIN[5] => Mux2.IN9
PBIN[6] => Mux1.IN9
PBIN[7] => Mux0.IN9
PortCStatus[0] => Mux7.IN10
PortCStatus[1] => Mux6.IN10
PortCStatus[2] => Mux5.IN10
PortCStatus[3] => Mux4.IN10
PortCStatus[4] => Mux3.IN10
PortCStatus[5] => Mux2.IN10
PortCStatus[6] => Mux1.IN10
PortCStatus[7] => Mux0.IN10
DOUT[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
DOUT[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|A8255|cntl_log:I_cntl_log
RESET => ControlRegQ[0].PRESET
RESET => ControlRegQ[1].PRESET
RESET => ControlRegQ[2].ACLR
RESET => ControlRegQ[3].PRESET
RESET => ControlRegQ[4].PRESET
RESET => ControlRegQ[5].ACLR
RESET => ControlRegQ[6].ACLR
CLK => ControlRegQ[0].CLK
CLK => ControlRegQ[1].CLK
CLK => ControlRegQ[2].CLK
CLK => ControlRegQ[3].CLK
CLK => ControlRegQ[4].CLK
CLK => ControlRegQ[5].CLK
CLK => ControlRegQ[6].CLK
nCS => PortARead~0.IN0
nCS => ControlRegWrite~0.IN0
nCS => PortAOutLd~0.IN0
nCS => PortBOutLd~0.IN0
nCS => ControlLogicProc~0.IN0
nCS => ControlLogicProc~2.IN0
nRD => PortARead~0.IN1
nWR => ControlRegWrite~0.IN1
nWR => PortAOutLd~1.IN0
nWR => PortBOutLd~1.IN0
nWR => ControlLogicProc~5.IN0
nWR => ControlLogicProc~3.IN0
A[0] => PortARead~2.IN0
A[0] => PortAWrite~1.IN0
A[0] => Mux0.IN4
A[0] => Equal0.IN1
A[0] => Equal1.IN1
A[0] => ControlRegWrite~2.IN1
A[0] => PortBRead~0.IN0
A[0] => PortBWrite~0.IN0
A[0] => DOUTSelect[1].DATAIN
A[0] => Equal4.IN1
A[0] => Equal5.IN0
A[1] => PortARead~1.IN0
A[1] => PortAWrite~0.IN1
A[1] => Mux0.IN3
A[1] => Equal0.IN0
A[1] => Equal1.IN0
A[1] => ControlRegWrite~1.IN1
A[1] => DOUTSelect[2].DATAIN
A[1] => Equal4.IN0
A[1] => Equal5.IN1
DIN[0] => ControlRegQ[0].DATAIN
DIN[1] => Mux1.IN10
DIN[1] => Mux2.IN10
DIN[1] => Mux3.IN10
DIN[1] => Mux4.IN10
DIN[1] => Mux5.IN10
DIN[1] => Mux6.IN10
DIN[1] => Mux7.IN10
DIN[1] => Mux8.IN10
DIN[1] => ControlRegQ[1].DATAIN
DIN[2] => Mux1.IN9
DIN[2] => Mux2.IN9
DIN[2] => Mux3.IN9
DIN[2] => Mux4.IN9
DIN[2] => Mux5.IN9
DIN[2] => Mux6.IN9
DIN[2] => Mux7.IN9
DIN[2] => Mux8.IN9
DIN[2] => ControlRegQ[2].DATAIN
DIN[3] => Mux1.IN8
DIN[3] => Mux2.IN8
DIN[3] => Mux3.IN8
DIN[3] => Mux4.IN8
DIN[3] => Mux5.IN8
DIN[3] => Mux6.IN8
DIN[3] => Mux7.IN8
DIN[3] => Mux8.IN8
DIN[3] => ControlRegQ[3].DATAIN
DIN[4] => ControlRegQ[4].DATAIN
DIN[5] => ControlRegQ[5].DATAIN
DIN[6] => ControlRegQ[6].DATAIN
DIN[7] => ControlRegWrite.IN1
DIN[7] => ControlLogicProc~1.IN0
DIN[7] => ControlLogicProc~6.IN0
PCIN[0] => ~NO_FANOUT~
PCIN[1] => ~NO_FANOUT~
PCIN[2] => ~NO_FANOUT~
PCIN[3] => ~NO_FANOUT~
PCIN[4] => ~NO_FANOUT~
PCIN[5] => ~NO_FANOUT~
PCIN[6] => PAEN~0.DATAA
PCIN[7] => ~NO_FANOUT~
PAEN <= PAEN~1.DB_MAX_OUTPUT_PORT_TYPE
PBEN <= ControlRegQ[1].DB_MAX_OUTPUT_PORT_TYPE
PCEN[0] <= PCEN~4.DB_MAX_OUTPUT_PORT_TYPE
PCEN[1] <= PCEN~3.DB_MAX_OUTPUT_PORT_TYPE
PCEN[2] <= PCEN~2.DB_MAX_OUTPUT_PORT_TYPE
PCEN[3] <= PCEN~1.DB_MAX_OUTPUT_PORT_TYPE
PCEN[4] <= PCEN~16.DB_MAX_OUTPUT_PORT_TYPE
PCEN[5] <= PCEN~15.DB_MAX_OUTPUT_PORT_TYPE
PCEN[6] <= PCEN~14.DB_MAX_OUTPUT_PORT_TYPE
PCEN[7] <= PCEN~13.DB_MAX_OUTPUT_PORT_TYPE
DOUTSelect[0] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
DOUTSelect[1] <= A[0].DB_MAX_OUTPUT_PORT_TYPE
DOUTSelect[2] <= A[1].DB_MAX_OUTPUT_PORT_TYPE
ControlReg[0] <= ControlRegQ[0].DB_MAX_OUTPUT_PORT_TYPE
ControlReg[1] <= ControlRegQ[1].DB_MAX_OUTPUT_PORT_TYPE
ControlReg[2] <= ControlRegQ[2].DB_MAX_OUTPUT_PORT_TYPE
ControlReg[3] <= ControlRegQ[3].DB_MAX_OUTPUT_PORT_TYPE
ControlReg[4] <= ControlRegQ[4].DB_MAX_OUTPUT_PORT_TYPE
ControlReg[5] <= ControlRegQ[5].DB_MAX_OUTPUT_PORT_TYPE
ControlReg[6] <= ControlRegQ[6].DB_MAX_OUTPUT_PORT_TYPE
ControlReg[7] <= <VCC>
PortARead <= PortARead~2.DB_MAX_OUTPUT_PORT_TYPE
PortBRead <= PortBRead~0.DB_MAX_OUTPUT_PORT_TYPE
PortAWrite <= PortAWrite~1.DB_MAX_OUTPUT_PORT_TYPE
PortBWrite <= PortBWrite~0.DB_MAX_OUTPUT_PORT_TYPE
PortAOutLd <= PortAOutLd~1.DB_MAX_OUTPUT_PORT_TYPE