a8255.tan.qmsg

8255并行接口芯片得VHDL描述

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DOUT\[4\] cntl_log:I_cntl_log\|ControlRegQ\[6\] 13.487 ns register " "Info: tco from clock \"CLK\" to destination pin \"DOUT\[4\]\" through register \"cntl_log:I_cntl_log\|ControlRegQ\[6\]\" is 13.487 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.023 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.023 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 54 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.653 ns) + CELL(0.542 ns) 3.023 ns cntl_log:I_cntl_log\|ControlRegQ\[6\] 2 REG LC_X33_Y16_N0 16 " "Info: 2: + IC(1.653 ns) + CELL(0.542 ns) = 3.023 ns; Loc. = LC_X33_Y16_N0; Fanout = 16; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[6\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.195 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 220 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.32 % ) " "Info: Total cell delay = 1.370 ns ( 45.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.653 ns ( 54.68 % ) " "Info: Total interconnect delay = 1.653 ns ( 54.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 cntl_log:I_cntl_log|ControlRegQ[6] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 220 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.308 ns + Longest register pin " "Info: + Longest register to pin delay is 10.308 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cntl_log:I_cntl_log\|ControlRegQ\[6\] 1 REG LC_X33_Y16_N0 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y16_N0; Fanout = 16; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[6\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 220 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.075 ns) 0.469 ns cntl_log:I_cntl_log\|Mux0~87 2 COMB LC_X33_Y16_N4 3 " "Info: 2: + IC(0.394 ns) + CELL(0.075 ns) = 0.469 ns; Loc. = LC_X33_Y16_N4; Fanout = 3; COMB Node = 'cntl_log:I_cntl_log\|Mux0~87'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.469 ns" { cntl_log:I_cntl_log|ControlRegQ[6] cntl_log:I_cntl_log|Mux0~87 } "NODE_NAME" } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.280 ns) + CELL(0.183 ns) 1.932 ns cntl_log:I_cntl_log\|Mux0~88 3 COMB LC_X36_Y18_N4 12 " "Info: 3: + IC(1.280 ns) + CELL(0.183 ns) = 1.932 ns; Loc. = LC_X36_Y18_N4; Fanout = 12; COMB Node = 'cntl_log:I_cntl_log\|Mux0~88'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.463 ns" { cntl_log:I_cntl_log|Mux0~87 cntl_log:I_cntl_log|Mux0~88 } "NODE_NAME" } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.263 ns) + CELL(0.280 ns) 3.475 ns dout_mux:I_dout_mux\|Mux3~534 4 COMB LC_X33_Y17_N8 1 " "Info: 4: + IC(1.263 ns) + CELL(0.280 ns) = 3.475 ns; Loc. = LC_X33_Y17_N8; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~534'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.543 ns" { cntl_log:I_cntl_log|Mux0~88 dout_mux:I_dout_mux|Mux3~534 } "NODE_NAME" } } { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.366 ns) 4.172 ns dout_mux:I_dout_mux\|Mux3~535 5 COMB LC_X33_Y17_N6 1 " "Info: 5: + IC(0.331 ns) + CELL(0.366 ns) = 4.172 ns; Loc. = LC_X33_Y17_N6; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~535'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.697 ns" { dout_mux:I_dout_mux|Mux3~534 dout_mux:I_dout_mux|Mux3~535 } "NODE_NAME" } } { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.280 ns) 4.766 ns dout_mux:I_dout_mux\|Mux3~539 6 COMB LC_X33_Y17_N3 1 " "Info: 6: + IC(0.314 ns) + CELL(0.280 ns) = 4.766 ns; Loc. = LC_X33_Y17_N3; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~539'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.594 ns" { dout_mux:I_dout_mux|Mux3~535 dout_mux:I_dout_mux|Mux3~539 } "NODE_NAME" } } { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.855 ns) + CELL(2.687 ns) 10.308 ns DOUT\[4\] 7 PIN PIN_C13 0 " "Info: 7: + IC(2.855 ns) + CELL(2.687 ns) = 10.308 ns; Loc. = PIN_C13; Fanout = 0; PIN Node = 'DOUT\[4\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.542 ns" { dout_mux:I_dout_mux|Mux3~539 DOUT[4] } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.871 ns ( 37.55 % ) " "Info: Total cell delay = 3.871 ns ( 37.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.437 ns ( 62.45 % ) " "Info: Total interconnect delay = 6.437 ns ( 62.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "10.308 ns" { cntl_log:I_cntl_log|ControlRegQ[6] cntl_log:I_cntl_log|Mux0~87 cntl_log:I_cntl_log|Mux0~88 dout_mux:I_dout_mux|Mux3~534 dout_mux:I_dout_mux|Mux3~535 dout_mux:I_dout_mux|Mux3~539 DOUT[4] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "10.308 ns" { cntl_log:I_cntl_log|ControlRegQ[6] cntl_log:I_cntl_log|Mux0~87 cntl_log:I_cntl_log|Mux0~88 dout_mux:I_dout_mux|Mux3~534 dout_mux:I_dout_mux|Mux3~535 dout_mux:I_dout_mux|Mux3~539 DOUT[4] } { 0.000ns 0.394ns 1.280ns 1.263ns 0.331ns 0.314ns 2.855ns } { 0.000ns 0.075ns 0.183ns 0.280ns 0.366ns 0.280ns 2.687ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.023 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.023 ns" { CLK CLK~out0 cntl_log:I_cntl_log|ControlRegQ[6] } { 0.000ns 0.000ns 1.653ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "10.308 ns" { cntl_log:I_cntl_log|ControlRegQ[6] cntl_log:I_cntl_log|Mux0~87 cntl_log:I_cntl_log|Mux0~88 dout_mux:I_dout_mux|Mux3~534 dout_mux:I_dout_mux|Mux3~535 dout_mux:I_dout_mux|Mux3~539 DOUT[4] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "10.308 ns" { cntl_log:I_cntl_log|ControlRegQ[6] cntl_log:I_cntl_log|Mux0~87 cntl_log:I_cntl_log|Mux0~88 dout_mux:I_dout_mux|Mux3~534 dout_mux:I_dout_mux|Mux3~535 dout_mux:I_dout_mux|Mux3~539 DOUT[4] } { 0.000ns 0.394ns 1.280ns 1.263ns 0.331ns 0.314ns 2.855ns } { 0.000ns 0.075ns 0.183ns 0.280ns 0.366ns 0.280ns 2.687ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A\[0\] DOUT\[4\] 14.138 ns Longest " "Info: Longest tpd from source pin \"A\[0\]\" to destination pin \"DOUT\[4\]\" is 14.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns A\[0\] 1 PIN PIN_B8 31 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B8; Fanout = 31; PIN Node = 'A\[0\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { A[0] } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.395 ns) + CELL(0.280 ns) 5.762 ns cntl_log:I_cntl_log\|Mux0~88 2 COMB LC_X36_Y18_N4 12 " "Info: 2: + IC(4.395 ns) + CELL(0.280 ns) = 5.762 ns; Loc. = LC_X36_Y18_N4; Fanout = 12; COMB Node = 'cntl_log:I_cntl_log\|Mux0~88'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.675 ns" { A[0] cntl_log:I_cntl_log|Mux0~88 } "NODE_NAME" } } { "cntl_log.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/cntl_log.vhd" 144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.263 ns) + CELL(0.280 ns) 7.305 ns dout_mux:I_dout_mux\|Mux3~534 3 COMB LC_X33_Y17_N8 1 " "Info: 3: + IC(1.263 ns) + CELL(0.280 ns) = 7.305 ns; Loc. = LC_X33_Y17_N8; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~534'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.543 ns" { cntl_log:I_cntl_log|Mux0~88 dout_mux:I_dout_mux|Mux3~534 } "NODE_NAME" } } { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.331 ns) + CELL(0.366 ns) 8.002 ns dout_mux:I_dout_mux\|Mux3~535 4 COMB LC_X33_Y17_N6 1 " "Info: 4: + IC(0.331 ns) + CELL(0.366 ns) = 8.002 ns; Loc. = LC_X33_Y17_N6; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~535'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.697 ns" { dout_mux:I_dout_mux|Mux3~534 dout_mux:I_dout_mux|Mux3~535 } "NODE_NAME" } } { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.280 ns) 8.596 ns dout_mux:I_dout_mux\|Mux3~539 5 COMB LC_X33_Y17_N3 1 " "Info: 5: + IC(0.314 ns) + CELL(0.280 ns) = 8.596 ns; Loc. = LC_X33_Y17_N3; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~539'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.594 ns" { dout_mux:I_dout_mux|Mux3~535 dout_mux:I_dout_mux|Mux3~539 } "NODE_NAME" } } { "dout_mux.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/dout_mux.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.855 ns) + CELL(2.687 ns) 14.138 ns DOUT\[4\] 6 PIN PIN_C13 0 " "Info: 6: + IC(2.855 ns) + CELL(2.687 ns) = 14.138 ns; Loc. = PIN_C13; Fanout = 0; PIN Node = 'DOUT\[4\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "5.542 ns" { dout_mux:I_dout_mux|Mux3~539 DOUT[4] } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.980 ns ( 35.22 % ) " "Info: Total cell delay = 4.980 ns ( 35.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.158 ns ( 64.78 % ) " "Info: Total interconnect delay = 9.158 ns ( 64.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "14.138 ns" { A[0] cntl_log:I_cntl_log|Mux0~88 dout_mux:I_dout_mux|Mux3~534 dout_mux:I_dout_mux|Mux3~535 dout_mux:I_dout_mux|Mux3~539 DOUT[4] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "14.138 ns" { A[0] A[0]~out0 cntl_log:I_cntl_log|Mux0~88 dout_mux:I_dout_mux|Mux3~534 dout_mux:I_dout_mux|Mux3~535 dout_mux:I_dout_mux|Mux3~539 DOUT[4] } { 0.000ns 0.000ns 4.395ns 1.263ns 0.331ns 0.314ns 2.855ns } { 0.000ns 1.087ns 0.280ns 0.280ns 0.366ns 0.280ns 2.687ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "portain:I_portain\|PortAInRegQ\[6\] PAIN\[6\] CLK -1.819 ns register " "Info: th for register \"portain:I_portain\|PortAInRegQ\[6\]\" (data pin = \"PAIN\[6\]\", clock pin = \"CLK\") is -1.819 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.029 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 54 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.659 ns) + CELL(0.542 ns) 3.029 ns portain:I_portain\|PortAInRegQ\[6\] 2 REG LC_X33_Y18_N2 1 " "Info: 2: + IC(1.659 ns) + CELL(0.542 ns) = 3.029 ns; Loc. = LC_X33_Y18_N2; Fanout = 1; REG Node = 'portain:I_portain\|PortAInRegQ\[6\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.201 ns" { CLK portain:I_portain|PortAInRegQ[6] } "NODE_NAME" } } { "portain.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portain.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.23 % ) " "Info: Total cell delay = 1.370 ns ( 45.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns ( 54.77 % ) " "Info: Total interconnect delay = 1.659 ns ( 54.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.029 ns" { CLK portain:I_portain|PortAInRegQ[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.029 ns" { CLK CLK~out0 portain:I_portain|PortAInRegQ[6] } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "portain.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portain.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.948 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.948 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns PAIN\[6\] 1 PIN PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L1; Fanout = 2; PIN Node = 'PAIN\[6\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { PAIN[6] } "NODE_NAME" } } { "A8255.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/A8255.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.138 ns) + CELL(0.085 ns) 4.948 ns portain:I_portain\|PortAInRegQ\[6\] 2 REG LC_X33_Y18_N2 1 " "Info: 2: + IC(4.138 ns) + CELL(0.085 ns) = 4.948 ns; Loc. = LC_X33_Y18_N2; Fanout = 1; REG Node = 'portain:I_portain\|PortAInRegQ\[6\]'" {  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.223 ns" { PAIN[6] portain:I_portain|PortAInRegQ[6] } "NODE_NAME" } } { "portain.vhd" "" { Text "D:/EDAtool/altera/Design_ok/PALIC_8255/portain.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.810 ns ( 16.37 % ) " "Info: Total cell delay = 0.810 ns ( 16.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.138 ns ( 83.63 % ) " "Info: Total interconnect delay = 4.138 ns ( 83.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.948 ns" { PAIN[6] portain:I_portain|PortAInRegQ[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "4.948 ns" { PAIN[6] PAIN[6]~out0 portain:I_portain|PortAInRegQ[6] } { 0.000ns 0.000ns 4.138ns } { 0.000ns 0.725ns 0.085ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.029 ns" { CLK portain:I_portain|PortAInRegQ[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "3.029 ns" { CLK CLK~out0 portain:I_portain|PortAInRegQ[6] } { 0.000ns 0.000ns 1.659ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/edatool/altera/quartus6.0/win/TimingClosureFloorplan.fld" "" "4.948 ns" { PAIN[6] portain:I_portain|PortAInRegQ[6] } "NODE_NAME" } } { "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/edatool/altera/quartus6.0/win/Technology_Viewer.qrui" "4.948 ns" { PAIN[6] PAIN[6]~out0 portain:I_portain|PortAInRegQ[6] } { 0.000ns 0.000ns 4.138ns } { 0.000ns 0.725ns 0.085ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}