sd_if.fit.summary

来自「8读8写SDRAM verilog 程序」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Thu Jan 24 21:31:01 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : sd_if
Top-level Entity Name : sd_if
Family : Stratix
Device : EP1S25F780I6
Timing Models : Final
Total logic elements : 107 / 25,660 ( < 1 % )
Total pins : 97 / 598 ( 16 % )
Total virtual pins : 0
Total memory bits : 0 / 1,944,576 ( 0 % )
DSP block 9-bit elements : 0 / 80 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )