mem_ctrl1.fit.summary

8读8写SDRAM verilog 程序

Fitter Status : Failed - Thu Jan 24 21:28:11 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : mem_ctrl1
Top-level Entity Name : mem_ctrl1
Family : Stratix
Device : EP1S25F780I6
Timing Models : Final
Total logic elements : 83 / 25,660 ( < 1 % )
Total pins : 1,833 / 598 ( 307 % )
Total virtual pins : 0
Total memory bits : 384 / 1,944,576 ( < 1 % )
DSP block 9-bit elements : 0 / 80 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )