sd_top.map.summary

8读8写SDRAM verilog 程序

Analysis & Synthesis Status : Successful - Thu Jan 24 21:35:14 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : sd_top
Top-level Entity Name : sd_if
Family : FLEX10K
Total logic elements : 101
Total pins : 97
Total memory bits : 0