sd_if.map.summary

8读8写SDRAM verilog 程序

Analysis & Synthesis Status : Successful - Thu Jan 24 21:37:57 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : sd_if
Top-level Entity Name : sd_if
Family : Stratix
Total logic elements : 109
Total pins : 97
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0