📄 matrix_op.v
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module matrix_op( clk,reset,bit_in,bit_in_en, media_in,media_in_en,
coder_first,
bit_out,bit_out_en, first_out,
data_out);
input clk,reset;
input bit_in,bit_in_en;
input[126:0] media_in;
input media_in_en;
input coder_first; //每一组编码第一个数据输入指示，便于处理相乘后直接存储到out，不必异或
output[126:0] data_out;
//output data_out_en;
output bit_out;
output bit_out_en;
output first_out;
reg first_out;
reg[126:0] media;
reg bit_out;
reg bit_out_en;
reg[126:0] data_out;
//reg data_out_en;
always @(posedge clk)
begin
if (!reset)
begin
media <= 127'd0;
data_out <= 127'd0;
//data_out_en <= 1'b0;
bit_out <= 1'b0;
bit_out_en <= 1'b0;
end
else
begin
if (bit_in_en)
begin
if(coder_first)
begin
if(bit_in)
begin
data_out <= media;
end
else
begin
data_out <= 127'd0;
end
end
else
begin
if(bit_in)
begin
data_out <= data_out^media;
end
end
/* if(coder_last)
begin
data_out_en <= 1'b1;
end
else
begin
data_out_en <= 1'b0;
end
*/
media <= {media[0],media[126:1]};
first_out <= coder_first;
bit_out <= bit_in;
bit_out_en <= 1'b1;
end
else
begin
bit_out_en<=1'b0;
//data_out_en <= 1'b0;
end
if(media_in_en) //外部保证第127个符号输入时同步输入media初始信息
begin
media <= media_in;
end
end
end
endmodule
module LDPC (clk,reset,
data_in, data_in_en,
velocity, /*输入信号码率选择*/
data_out, data_out_en,
indication /*输出信号，第一个127要删除前5成7488，指示第一个127*/
);
input clk,reset;
input data_in,data_in_en;
input[1:0] velocity; //码率选择信号
output[126:0] data_out;//输出信号
output data_out_en;
output indication;
parameter row_4 = 6'd24-1'b1; // parameter column_4 = 6'd35-1'b1; //0.4码率
parameter row_6 = 6'd36-1'b1; // parameter column_6 = 6'd23-1'b1; //0.6码率
parameter row_8 = 6'd48-1'b1; // parameter column_8 = 6'd11-1'b1; //0.8码率
parameter order = 7'd127-1'b1;
parameter state0 = 1'b0; parameter state1 = 1'b1;
reg[5:0] row_num; // reg[5:0] column_num;//reset时，选择合适的行，列数
reg[5:0] count_row; // reg[4:0] count_col; // 行列计数器
reg[6:0] count_127;
reg coder_first;
always @ (posedge clk) // 计数器运转
begin
if (!reset)
begin
count_127 <= 7'd0;
coder_first <= 1'b0;
case (velocity)
2'b01 : //0.4码率
begin
count_row <= 6'd23; // 减法计数器
row_num <= row_4;
//column_num <= column_4;
end
2'b10 : //0.6码率
begin
count_row <= 6'd35;
row_num <= row_6;
//column_num <= column_6;
end
2'b11 : //0.8码率
begin
count_row <= 6'd47;
row_num <= row_8;
//column_num <= column_8;
end
default : // 默认0.4码率
begin
count_row <= 6'd23;
row_num <= row_4;
//column_num <= column_4;
end
endcase
end
else
begin
if(data_in_en)
begin
case (velocity)
2'b01 : //0.4码率
begin
if((count_row==6'd23)&&(count_127==0))
begin
coder_first<= 1'b1;
end
else
begin
coder_first<= 1'b0;
end
end
2'b10 : //0.6码率
begin
if((count_row==6'd35)&&(count_127==0))
begin
coder_first<= 1'b1;
end
else
begin
coder_first<= 1'b0;
end
end
2'b11 : //0.8码率
begin
if((count_row==6'd47)&&(count_127==0))
begin
coder_first<= 1'b1;
end
else
begin
coder_first<= 1'b0;
end
end
default : // 默认0.4码率
begin
if((count_row==6'd23)&&(count_127==0))
begin
coder_first<= 1'b1;
end
else
begin
coder_first<= 1'b0;
end
end
endcase
if(count_127 == order)
begin
count_127 <= 7'd0;
if(count_row == 6'd0)
begin
count_row <= row_num;
end
else
begin
count_row <= count_row - 1'b1;
end
end
else
begin
count_127 <= count_127 + 1'b1;
end
end
end
end
reg bit_in, bit_in_en;
reg[34:0] media_en;
reg[34:0] media_en0;
reg state;
reg[9:0] address_04;
reg[9:0] address_06;
reg[9:0] address_08;
always @(posedge clk) // 控制个运算模块初始化等
begin
if (!reset)
begin
//coder_first <= 1'b0;
bit_in <= 1'b0; bit_in_en <= 1'b0;
media_en <= 35'b00000_0000000000_0000000000_0000000001; // 初始化时就写入第一个media
address_04 <= 10'd0; address_06 <= 10'd0; address_08 <= 10'd0;
state <= state0;
end
else
begin
case (velocity)
2'b01 : // 0.4 码率
begin
bit_in <= data_in; bit_in_en <= data_in_en; // 输入数据
if(data_in_en)
begin
case (state)
state0 : //前35个符号，需要按顺序对media写初始信息
begin
if(media_en == 35'b10000_0000000000_0000000000_0000000000)
begin
state <= state1;
media_en <= 35'd0;
if(count_row == 0) //最后一行最后一个矩信息，复位rom地址
begin
address_04 <= 10'd0;
end
else
begin
address_04 <= address_04+1'b1;
end
end
else
begin
address_04 <= address_04+1'b1; // 状态地址累加
media_en <= media_en << 1; //按顺序更改35个运算模块的media_en，写入初始信息
end
end
state1 : // 后面输入数据，循环运算即可，不需写矩阵初始信息
begin
if(count_127 == order)
begin
media_en <= 35'b00000_0000000000_0000000000_0000000001; //与第127个数据输入同时，写入初始信息
state <= state0;
end
end
endcase
end
end
2'b10 : // 0.6码率
begin
bit_in <= data_in; bit_in_en <= data_in_en; // 输入数据
if(data_in_en)
begin
case (state)
state0 : //前23个符号，需要按顺序对media写初始信息
begin
if(media_en == 35'b00000_0000000100_0000000000_0000000000)
begin
state <= state1;
media_en <= 35'd0;
if(count_row == 0) //最后一行最后一个矩信息，复位rom地址
begin
address_06 <= 10'd0;
end
else
begin
address_06 <= address_06+1'b1;
end
end
else
begin
address_06 <= address_06+1'b1; // 状态地址累加
media_en <= media_en << 1; //按顺序更改35个运算模块的media_en，写入初始信息
end
end
state1 : // 后面输入数据，循环运算即可，不需写矩阵初始信息
begin
if(count_127 == order)
begin
media_en <= 35'b00000_0000000000_0000000000_0000000001; //与第127个数据输入同时，写入初始信息
state <= state0;
end
end
endcase
end
end
2'b11 :
begin
bit_in <= data_in; bit_in_en <= data_in_en; // 输入数据
if(data_in_en)
begin
case (state)
state0 : //前35个符号，需要按顺序对media写初始信息
begin
if(media_en == 35'b00000_000000000_0000000001_0000000000)
begin
state <= state1;
media_en <= 35'd0;
if(count_row == 0) //最后一行最后一个矩信息，复位rom地址
begin
address_08 <= 10'd0;
end
else
begin
address_08 <= address_08+1'b1;
end
end
else
begin
address_08 <= address_08+1'b1; // 状态地址累加
media_en <= media_en << 1; //按顺序更改35个运算模块的media_en，写入初始信息
end
end
state1 : // 后面输入数据，循环运算即可，不需写矩阵初始信息
begin
if(count_127 == order)
begin
media_en <= 35'b00000_0000000000_0000000000_0000000001; //与第127个数据输入同时，写入初始信息
state <= state0;
end
end
endcase
end
end
default :
begin
bit_in <= data_in; bit_in_en <= data_in_en; // 输入数据
if(data_in_en)
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