rs_5_3_codec.vo

学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字

defparam \SYND2_[3]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC2_A35
flex10ke_lcell \m0_|i13~13_I (
// Equation(s):
// \m0_|i13~13  = \SYND2_[6]  $ \SYND2_[1]  $ \SYND2_[5]  $ \SYND2_[3] 

	.dataa(\SYND2_[6] ),
	.datab(\SYND2_[1] ),
	.datac(\SYND2_[5] ),
	.datad(\SYND2_[3] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\m0_|i13~13 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \m0_|i13~13_I .operation_mode = "normal";
defparam \m0_|i13~13_I .packed_mode = "false";
defparam \m0_|i13~13_I .lut_mask = "6996";
defparam \m0_|i13~13_I .clock_enable_mode = "false";
defparam \m0_|i13~13_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC1_A28
flex10ke_lcell \i15~288_I (
// Equation(s):
// \i15~288  = \m0_|i13~13  $ (\SYND1_[4]  & \E_D~dataout )

	.dataa(vcc),
	.datab(\SYND1_[4] ),
	.datac(\E_D~dataout ),
	.datad(\m0_|i13~13 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i15~288 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \i15~288_I .operation_mode = "normal";
defparam \i15~288_I .packed_mode = "false";
defparam \i15~288_I .lut_mask = "3FC0";
defparam \i15~288_I .clock_enable_mode = "false";
defparam \i15~288_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC5_D34
flex10ke_lcell \i393~178_I (
// Equation(s):
// \i393~178  = \DATA_IN[4]~dataout  $ (\i15~288  & \i~10 )

	.dataa(vcc),
	.datab(\i15~288 ),
	.datac(\i~10 ),
	.datad(\DATA_IN[4]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i393~178 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \i393~178_I .operation_mode = "normal";
defparam \i393~178_I .packed_mode = "false";
defparam \i393~178_I .lut_mask = "3FC0";
defparam \i393~178_I .clock_enable_mode = "false";
defparam \i393~178_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC4_D34
flex10ke_lcell \SYND2_[4]~I (
// Equation(s):
// \SYND2_[4]  = DFFEA(\DATA_VALID_IN~dataout  & !\i124~44  & \SYND2_[4]  # !\DATA_VALID_IN~dataout  & \i393~178 , GLOBAL(\CLK~dataout ), GLOBAL(\RESET~dataout ), , , , )

	.dataa(\i124~44 ),
	.datab(\DATA_VALID_IN~dataout ),
	.datac(\SYND2_[4] ),
	.datad(\i393~178 ),
	.aclr(!\RESET~dataout ),
	.aload(gnd),
	.clk(\CLK~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SYND2_[4] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \SYND2_[4]~I .operation_mode = "normal";
defparam \SYND2_[4]~I .packed_mode = "false";
defparam \SYND2_[4]~I .lut_mask = "7340";
defparam \SYND2_[4]~I .clock_enable_mode = "false";
defparam \SYND2_[4]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at Pin_125
flex10ke_io \DATA_IN[5]~I (
	.datain(),
	.clk(),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\DATA_IN[5]~dataout ),
	.padio(DATA_IN[5]));
// synopsys translate_off
defparam \DATA_IN[5]~I .operation_mode = "input";
defparam \DATA_IN[5]~I .reg_source_mode = "none";
defparam \DATA_IN[5]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at LC3_C10
flex10ke_lcell \i384~397_I (
// Equation(s):
// \i384~397  = \SYND1_[5]  $ (!\i14~288  # !\i124~44 ) # !\DATA_VALID_IN~dataout 

	.dataa(\DATA_VALID_IN~dataout ),
	.datab(\SYND1_[5] ),
	.datac(\i124~44 ),
	.datad(\i14~288 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(),
	.cout(),
	.cascout(\i384~397 ));
// synopsys translate_off
defparam \i384~397_I .operation_mode = "normal";
defparam \i384~397_I .packed_mode = "false";
defparam \i384~397_I .lut_mask = "D777";
defparam \i384~397_I .clock_enable_mode = "false";
defparam \i384~397_I .output_mode = "none";
// synopsys translate_on

// atom is at LC4_C10
flex10ke_lcell \i384~399_I (
// Equation(s):
// \i384~399  = (\DATA_VALID_IN~dataout  # \DATA_IN[5]~dataout  $ (!\i~10  # !\SYND1_[5] )) & CASCADE(\i384~397 )

	.dataa(\DATA_IN[5]~dataout ),
	.datab(\SYND1_[5] ),
	.datac(\i~10 ),
	.datad(\DATA_VALID_IN~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(\i384~397 ),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i384~399 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \i384~399_I .operation_mode = "normal";
defparam \i384~399_I .packed_mode = "false";
defparam \i384~399_I .lut_mask = "FF95";
defparam \i384~399_I .clock_enable_mode = "false";
defparam \i384~399_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC5_C10
flex10ke_lcell \SYND1_[5]~I (
// Equation(s):
// \SYND1_[5]  = DFFEA(!\i384~399 , GLOBAL(\CLK~dataout ), GLOBAL(\RESET~dataout ), , , , )

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\i384~399 ),
	.aclr(!\RESET~dataout ),
	.aload(gnd),
	.clk(\CLK~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SYND1_[5] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \SYND1_[5]~I .operation_mode = "normal";
defparam \SYND1_[5]~I .packed_mode = "false";
defparam \SYND1_[5]~I .lut_mask = "00FF";
defparam \SYND1_[5]~I .clock_enable_mode = "false";
defparam \SYND1_[5]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC4_C11
flex10ke_lcell \i14~288_I (
// Equation(s):
// \i14~288  = \m0_|i10~26  $ \SYND2_[4]  $ (\SYND1_[5]  & \E_D~dataout )

	.dataa(\m0_|i10~26 ),
	.datab(\SYND2_[4] ),
	.datac(\SYND1_[5] ),
	.datad(\E_D~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i14~288 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \i14~288_I .operation_mode = "normal";
defparam \i14~288_I .packed_mode = "false";
defparam \i14~288_I .lut_mask = "9666";
defparam \i14~288_I .clock_enable_mode = "false";
defparam \i14~288_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC2_D2
flex10ke_lcell \i392~179_I (
// Equation(s):
// \i392~179  = \DATA_IN[5]~dataout  $ (\i14~288  & \i~10 )

	.dataa(vcc),
	.datab(\i14~288 ),
	.datac(\i~10 ),
	.datad(\DATA_IN[5]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i392~179 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \i392~179_I .operation_mode = "normal";
defparam \i392~179_I .packed_mode = "false";
defparam \i392~179_I .lut_mask = "3FC0";
defparam \i392~179_I .clock_enable_mode = "false";
defparam \i392~179_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC2_D31
flex10ke_lcell \SYND2_[5]~I (
// Equation(s):
// \SYND2_[5]  = DFFEA(\DATA_VALID_IN~dataout  & !\i124~44  & \SYND2_[5]  # !\DATA_VALID_IN~dataout  & \i392~179 , GLOBAL(\CLK~dataout ), GLOBAL(\RESET~dataout ), , , , )

	.dataa(\i124~44 ),
	.datab(\DATA_VALID_IN~dataout ),
	.datac(\SYND2_[5] ),
	.datad(\i392~179 ),
	.aclr(!\RESET~dataout ),
	.aload(gnd),
	.clk(\CLK~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SYND2_[5] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \SYND2_[5]~I .operation_mode = "normal";
defparam \SYND2_[5]~I .packed_mode = "false";
defparam \SYND2_[5]~I .lut_mask = "7340";
defparam \SYND2_[5]~I .clock_enable_mode = "false";
defparam \SYND2_[5]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC1_C16
flex10ke_lcell \m0_|i20~I (
// Equation(s):
// \m0_|i20  = \SYND2_[5]  $ \SYND2_[3]  $ \SYND2_[7] 

	.dataa(vcc),
	.datab(\SYND2_[5] ),
	.datac(\SYND2_[3] ),
	.datad(\SYND2_[7] ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\m0_|i20 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \m0_|i20~I .operation_mode = "normal";
defparam \m0_|i20~I .packed_mode = "false";
defparam \m0_|i20~I .lut_mask = "C33C";
defparam \m0_|i20~I .clock_enable_mode = "false";
defparam \m0_|i20~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC4_C16
flex10ke_lcell \i13~204_I (
// Equation(s):
// \i13~204  = \m0_|i20  $ (\SYND1_[6]  & \E_D~dataout )

	.dataa(vcc),
	.datab(\SYND1_[6] ),
	.datac(\E_D~dataout ),
	.datad(\m0_|i20 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i13~204 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \i13~204_I .operation_mode = "normal";
defparam \i13~204_I .packed_mode = "false";
defparam \i13~204_I .lut_mask = "3FC0";
defparam \i13~204_I .clock_enable_mode = "false";
defparam \i13~204_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC8_C16
flex10ke_lcell \i391~178_I (
// Equation(s):
// \i391~178  = \DATA_IN[6]~dataout  $ (\i13~204  & \i~10 )

	.dataa(vcc),
	.datab(\i13~204 ),
	.datac(\i~10 ),
	.datad(\DATA_IN[6]~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i391~178 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \i391~178_I .operation_mode = "normal";
defparam \i391~178_I .packed_mode = "false";
defparam \i391~178_I .lut_mask = "3FC0";
defparam \i391~178_I .clock_enable_mode = "false";
defparam \i391~178_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC1_C30
flex10ke_lcell \SYND2_[6]~I (
// Equation(s):
// \SYND2_[6]  = DFFEA(\DATA_VALID_IN~dataout  & !\i124~44  & \SYND2_[6]  # !\DATA_VALID_IN~dataout  & \i391~178 , GLOBAL(\CLK~dataout ), GLOBAL(\RESET~dataout ), , , , )

	.dataa(\i124~44 ),
	.datab(\DATA_VALID_IN~dataout ),
	.datac(\SYND2_[6] ),
	.datad(\i391~178 ),
	.aclr(!\RESET~dataout ),
	.aload(gnd),
	.clk(\CLK~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SYND2_[6] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \SYND2_[6]~I .operation_mode = "normal";
defparam \SYND2_[6]~I .packed_mode = "false";
defparam \SYND2_[6]~I .lut_mask = "7340";
defparam \SYND2_[6]~I .clock_enable_mode = "false";
defparam \SYND2_[6]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at Pin_56
flex10ke_io \DATA_IN[7]~I (
	.datain(),
	.clk(),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\DATA_IN[7]~dataout ),
	.padio(DATA_IN[7]));
// synopsys translate_off
defparam \DATA_IN[7]~I .operation_mode = "input";
defparam \DATA_IN[7]~I .reg_source_mode = "none";
defparam \DATA_IN[7]~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at LC7_C13
flex10ke_lcell \i382~734_I (
// Equation(s):
// \i382~734  = \SYND1_[7]  $ (!\i12~110  # !\i124~44 ) # !\DATA_VALID_IN~dataout 

	.dataa(\DATA_VALID_IN~dataout ),
	.datab(\SYND1_[7] ),
	.datac(\i124~44 ),
	.datad(\i12~110 ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(),
	.cout(),
	.cascout(\i382~734 ));
// synopsys translate_off
defparam \i382~734_I .operation_mode = "normal";
defparam \i382~734_I .packed_mode = "false";
defparam \i382~734_I .lut_mask = "D777";
defparam \i382~734_I .clock_enable_mode = "false";
defparam \i382~734_I .output_mode = "none";
// synopsys translate_on

// atom is at LC8_C13
flex10ke_lcell \i382~736_I (
// Equation(s):
// \i382~736  = (\DATA_VALID_IN~dataout  # \DATA_IN[7]~dataout  $ (!\i~10  # !\SYND1_[7] )) & CASCADE(\i382~734 )

	.dataa(\DATA_IN[7]~dataout ),
	.datab(\SYND1_[7] ),
	.datac(\i~10 ),
	.datad(\DATA_VALID_IN~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(),
	.cin(gnd),
	.cascin(\i382~734 ),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\i382~736 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \i382~736_I .operation_mode = "normal";
defparam \i382~736_I .packed_mode = "false";
defparam \i382~736_I .lut_mask = "FF95";
defparam \i382~736_I .clock_enable_mode = "false";
defparam \i382~736_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC6_C13
flex10ke_lcell \SYND1_[7]~I (
// Equation(s):
// \SYND1_[7]  = DFFEA(!\i382~736 , GLOBAL(\CLK~dataout ), GLOBAL(\RESET~dataout ), , , , )

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\i382~736 ),
	.aclr(!\RESET~dataout ),
	.aload(gnd),
	.clk(\CLK~dataout ),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\SYND1_[7] ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \SYND1_[7]~I .operation_mode = "normal";
defparam \SYND1_[7]~I .packed_mode = "false";
defparam \SYND1_[7]~I .lut_mask = "00FF";
defparam \SYND1_[7]~I .clock_