rs_5_3_codec.vo

学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.0 Build 190 1/28/2004 SJ Full Version"

// DATE "04/26/2005 21:43:30"

// 
// Device: Altera EPF10K30ETC144-1X Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog HDL output from Quartus II) only
// 

`timescale 1 ps/ 1 ps

module 	RS_5_3_CODEC (
	DATA_VALID_IN,
	E_D,
	CLK,
	RESET,
	DATA_IN,
	DATA_VALID_OUT,
	DATA_OUT);
input 	DATA_VALID_IN;
input 	E_D;
input 	CLK;
input 	RESET;
input 	[7:0] DATA_IN;
output 	DATA_VALID_OUT;
output 	[7:0] DATA_OUT;

supply0 gnd;
supply1 vcc;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("RS_5_3_CODEC_v.sdo");
// synopsys translate_on

wire \i184~184_1 ;
wire \i~698_1 ;
wire \i382~734_1 ;
wire \i383~397_1 ;
wire \i384~397_1 ;
wire \i385~397_1 ;
wire \i386~397_1 ;
wire \i387~733_1 ;
wire \i388~734_1 ;
wire \i389~733_1 ;
wire \DATA_VALID_IN~dataout ;
wire \E_D~dataout ;
wire \i~686 ;
wire \RESET~dataout ;
wire \CLK~dataout ;
wire \cntr1_[1] ;
wire \i~693 ;
wire \i~692 ;
wire \i~691 ;
wire \cntr1_[2] ;
wire \i~689 ;
wire \i~688 ;
wire \cntr1_[0] ;
wire \i~698 ;
wire \i~700 ;
wire \cntr1_[3] ;
wire \i124~44 ;
wire \cntr2_[1] ;
wire \cntr2_[2] ;
wire cntr2_en;
wire \cntr2_[0] ;
wire \i130~215 ;
wire \i130~213 ;
wire \i130~214 ;
wire \DATA_VALID_OUT~reg0 ;
wire \DATA_IN[0]~dataout ;
wire \i~10 ;
wire \DATA_IN[6]~dataout ;
wire \i383~397 ;
wire \i383~399 ;
wire \SYND1_[6] ;
wire \i397~178 ;
wire \SYND2_[0] ;
wire \DATA_IN[1]~dataout ;
wire \i388~734 ;
wire \i388~736 ;
wire \SYND1_[1] ;
wire \i18~110 ;
wire \i396~178 ;
wire \SYND2_[1] ;
wire \DATA_IN[2]~dataout ;
wire \i387~733 ;
wire \i387~735 ;
wire \SYND1_[2] ;
wire \i17~110 ;
wire \i395~178 ;
wire \SYND2_[2] ;
wire \m0_|i10~26 ;
wire \DATA_IN[4]~dataout ;
wire \i385~397 ;
wire \i385~399 ;
wire \SYND1_[4] ;
wire \DATA_IN[3]~dataout ;
wire \i386~397 ;
wire \i386~399 ;
wire \SYND1_[3] ;
wire \m0_|i10 ;
wire \i16~92 ;
wire \i394~178 ;
wire \SYND2_[3] ;
wire \m0_|i13~13 ;
wire \i15~288 ;
wire \i393~178 ;
wire \SYND2_[4] ;
wire \DATA_IN[5]~dataout ;
wire \i384~397 ;
wire \i384~399 ;
wire \SYND1_[5] ;
wire \i14~288 ;
wire \i392~179 ;
wire \SYND2_[5] ;
wire \m0_|i20 ;
wire \i13~204 ;
wire \i391~178 ;
wire \SYND2_[6] ;
wire \DATA_IN[7]~dataout ;
wire \i382~734 ;
wire \i382~736 ;
wire \SYND1_[7] ;
wire \i12~110 ;
wire \i390~178 ;
wire \SYND2_[7] ;
wire \i19~110 ;
wire \i389~733 ;
wire \i389~735 ;
wire \SYND1_[0] ;
wire \s_|inv_|i~437 ;
wire \s_|inv_|i~431 ;
wire \s_|inv_|i~433 ;
wire \s_|inv_|i~681 ;
wire \s_|inv_|i~435 ;
wire \s_|inv_|i~682 ;
wire \s_|inv_|i~413 ;
wire \s_|inv_|i~407 ;
wire \s_|inv_|i~409 ;
wire \s_|inv_|i~675 ;
wire \s_|inv_|i~411 ;
wire \s_|inv_|i~676 ;
wire \s_|inv_|i~421 ;
wire \s_|inv_|i~415 ;
wire \s_|inv_|i~417 ;
wire \s_|inv_|i~677 ;
wire \s_|inv_|i~419 ;
wire \s_|inv_|i~678 ;
wire \s_|inv_|i~623 ;
wire \s_|inv_|i~429 ;
wire \s_|inv_|i~423 ;
wire \s_|inv_|i~427 ;
wire \s_|inv_|i~679 ;
wire \s_|inv_|i~425 ;
wire \s_|inv_|i~680 ;
wire \s_|inv_|i~624 ;
wire \s_|inv_|i~469 ;
wire \s_|inv_|i~463 ;
wire \s_|inv_|i~465 ;
wire \s_|inv_|i~689 ;
wire \s_|inv_|i~467 ;
wire \s_|inv_|i~690 ;
wire \s_|inv_|i~445 ;
wire \s_|inv_|i~439 ;
wire \s_|inv_|i~441 ;
wire \s_|inv_|i~683 ;
wire \s_|inv_|i~443 ;
wire \s_|inv_|i~684 ;
wire \s_|inv_|i~453 ;
wire \s_|inv_|i~447 ;
wire \s_|inv_|i~449 ;
wire \s_|inv_|i~685 ;
wire \s_|inv_|i~451 ;
wire \s_|inv_|i~686 ;
wire \s_|inv_|i~625 ;
wire \s_|inv_|i~461 ;
wire \s_|inv_|i~455 ;
wire \s_|inv_|i~459 ;
wire \s_|inv_|i~687 ;
wire \s_|inv_|i~457 ;
wire \s_|inv_|i~688 ;
wire \s_|inv_|i~626 ;
wire \s_|mult_|i51~26 ;
wire \s_|inv_|i~247 ;
wire \s_|inv_|i~241 ;
wire \s_|inv_|i~245 ;
wire \s_|inv_|i~633 ;
wire \s_|inv_|i~243 ;
wire \s_|inv_|i~634 ;
wire \s_|inv_|i~223 ;
wire \s_|inv_|i~217 ;
wire \s_|inv_|i~219 ;
wire \s_|inv_|i~627 ;
wire \s_|inv_|i~221 ;
wire \s_|inv_|i~628 ;
wire \s_|inv_|i~231 ;
wire \s_|inv_|i~225 ;
wire \s_|inv_|i~227 ;
wire \s_|inv_|i~629 ;
wire \s_|inv_|i~229 ;
wire \s_|inv_|i~630 ;
wire \s_|inv_|i~611 ;
wire \s_|inv_|i~239 ;
wire \s_|inv_|i~233 ;
wire \s_|inv_|i~235 ;
wire \s_|inv_|i~631 ;
wire \s_|inv_|i~237 ;
wire \s_|inv_|i~632 ;
wire \s_|inv_|i~612 ;
wire \s_|inv_|i~279 ;
wire \s_|inv_|i~273 ;
wire \s_|inv_|i~275 ;
wire \s_|inv_|i~641 ;
wire \s_|inv_|i~277 ;
wire \s_|inv_|i~642 ;
wire \s_|inv_|i~255 ;
wire \s_|inv_|i~249 ;
wire \s_|inv_|i~253 ;
wire \s_|inv_|i~635 ;
wire \s_|inv_|i~251 ;
wire \s_|inv_|i~636 ;
wire \s_|inv_|i~263 ;
wire \s_|inv_|i~257 ;
wire \s_|inv_|i~261 ;
wire \s_|inv_|i~637 ;
wire \s_|inv_|i~259 ;
wire \s_|inv_|i~638 ;
wire \s_|inv_|i~613 ;
wire \s_|inv_|i~271 ;
wire \s_|inv_|i~265 ;
wire \s_|inv_|i~267 ;
wire \s_|inv_|i~639 ;
wire \s_|inv_|i~269 ;
wire \s_|inv_|i~640 ;
wire \s_|inv_|i~614 ;
wire \s_|mult_|i51~25 ;
wire \s_|inv_|i~405 ;
wire \s_|inv_|i~399 ;
wire \s_|inv_|i~403 ;
wire \s_|inv_|i~673 ;
wire \s_|inv_|i~401 ;
wire \s_|inv_|i~674 ;
wire \s_|inv_|i~381 ;
wire \s_|inv_|i~375 ;
wire \s_|inv_|i~377 ;
wire \s_|inv_|i~667 ;
wire \s_|inv_|i~379 ;
wire \s_|inv_|i~668 ;
wire \s_|inv_|i~389 ;
wire \s_|inv_|i~383 ;
wire \s_|inv_|i~385 ;
wire \s_|inv_|i~669 ;
wire \s_|inv_|i~387 ;
wire \s_|inv_|i~670 ;
wire \s_|inv_|i~621 ;
wire \s_|inv_|i~397 ;
wire \s_|inv_|i~391 ;
wire \s_|inv_|i~393 ;
wire \s_|inv_|i~671 ;
wire \s_|inv_|i~395 ;
wire \s_|inv_|i~672 ;
wire \s_|inv_|i~622 ;
wire \s_|mult_|i184~140 ;
wire \s_|mult_|i184~141 ;
wire \s_|inv_|i~373 ;
wire \s_|inv_|i~367 ;
wire \s_|inv_|i~369 ;
wire \s_|inv_|i~665 ;
wire \s_|inv_|i~371 ;
wire \s_|inv_|i~666 ;
wire \s_|inv_|i~349 ;
wire \s_|inv_|i~344 ;
wire \s_|inv_|i~731 ;
wire \s_|inv_|i~659 ;
wire \s_|inv_|i~347 ;
wire \s_|inv_|i~660 ;
wire \s_|inv_|i~357 ;
wire \s_|inv_|i~351 ;
wire \s_|inv_|i~355 ;
wire \s_|inv_|i~661 ;
wire \s_|inv_|i~353 ;
wire \s_|inv_|i~662 ;
wire \s_|inv_|i~619 ;
wire \s_|inv_|i~365 ;
wire \s_|inv_|i~359 ;
wire \s_|inv_|i~363 ;
wire \s_|inv_|i~663 ;
wire \s_|inv_|i~361 ;
wire \s_|inv_|i~664 ;
wire \s_|inv_|i~620 ;
wire \s_|mult_|i184~139 ;
wire \s_|inv_|i~730 ;
wire \s_|inv_|i~305 ;
wire \s_|inv_|i~307 ;
wire \s_|inv_|i~649 ;
wire \s_|inv_|i~309 ;
wire \s_|inv_|i~650 ;
wire \s_|inv_|i~287 ;
wire \s_|inv_|i~281 ;
wire \s_|inv_|i~285 ;
wire \s_|inv_|i~643 ;
wire \s_|inv_|i~283 ;
wire \s_|inv_|i~644 ;
wire \s_|inv_|i~303 ;
wire \s_|inv_|i~297 ;
wire \s_|inv_|i~299 ;
wire \s_|inv_|i~647 ;
wire \s_|inv_|i~301 ;
wire \s_|inv_|i~648 ;
wire \s_|inv_|i~615 ;
wire \s_|inv_|i~295 ;
wire \s_|inv_|i~289 ;
wire \s_|inv_|i~293 ;
wire \s_|inv_|i~645 ;
wire \s_|inv_|i~291 ;
wire \s_|inv_|i~646 ;
wire \s_|inv_|i~616 ;
wire \s_|inv_|i~342 ;
wire \s_|inv_|i~336 ;
wire \s_|inv_|i~340 ;
wire \s_|inv_|i~657 ;
wire \s_|inv_|i~338 ;
wire \s_|inv_|i~658 ;
wire \s_|inv_|i~318 ;
wire \s_|inv_|i~312 ;
wire \s_|inv_|i~316 ;
wire \s_|inv_|i~651 ;
wire \s_|inv_|i~314 ;
wire \s_|inv_|i~652 ;
wire \s_|inv_|i~326 ;
wire \s_|inv_|i~320 ;
wire \s_|inv_|i~324 ;
wire \s_|inv_|i~653 ;
wire \s_|inv_|i~322 ;
wire \s_|inv_|i~654 ;
wire \s_|inv_|i~617 ;
wire \s_|inv_|i~334 ;
wire \s_|inv_|i~328 ;
wire \s_|inv_|i~330 ;
wire \s_|inv_|i~655 ;
wire \s_|inv_|i~332 ;
wire \s_|inv_|i~656 ;
wire \s_|inv_|i~618 ;
wire \s_|mult_|i184~138 ;
wire \s_|mult_|i184~142 ;
wire \s_|mult_|i90~43 ;
wire \s_|mult_|i90~44 ;
wire \s_|mult_|i90~42 ;
wire \s_|mult_|i90~41 ;
wire \s_|mult_|i184~136 ;
wire \s_|mult_|i184~134 ;
wire \s_|mult_|i233 ;
wire \s_|mult_|i184~135 ;
wire \s_|mult_|i184~133 ;
wire \s_|mult_|i184~132 ;
wire \s_|mult_|i184~137 ;
wire \s_|mult_|i90 ;
wire \s_|i4 ;
wire \s_|mult_|i184~144 ;
wire \s_|mult_|i184~145 ;
wire \s_|mult_|i184~143 ;
wire \s_|mult_|i184~146 ;
wire \LOC2_[2] ;
wire \LOC2_[0] ;
wire \i184~183 ;
wire \LOC2_[1] ;
wire \i184~184 ;
wire \i184~186 ;
wire \i208~258 ;
wire \FIFO0_[7] ;
wire \FIFO1_[7] ;
wire \FIFO2_[7] ;
wire \FIFO3_[7] ;
wire \FIFO4_[7] ;
wire \i208~257 ;
wire \VAL[7] ;
wire \i184~3 ;
wire \i208~256 ;
wire \DATA_OUT[7]~reg0 ;
wire \FIFO0_[6] ;
wire \FIFO1_[6] ;
wire \FIFO2_[6] ;
wire \FIFO3_[6] ;
wire \FIFO4_[6] ;
wire \i209~192 ;
wire \VAL[6] ;
wire \i185~3 ;
wire \i209~191 ;
wire \DATA_OUT[6]~reg0 ;
wire \FIFO0_[5] ;
wire \FIFO1_[5] ;
wire \FIFO2_[5] ;
wire \FIFO3_[5] ;
wire \FIFO4_[5] ;
wire \i210~192 ;
wire \VAL[5] ;
wire \i186~3 ;
wire \i210~191 ;
wire \DATA_OUT[5]~reg0 ;
wire \FIFO0_[4] ;
wire \FIFO1_[4] ;
wire \FIFO2_[4] ;
wire \FIFO3_[4] ;
wire \FIFO4_[4] ;
wire \i211~192 ;
wire \VAL[4] ;
wire \i187~3 ;
wire \i211~191 ;
wire \DATA_OUT[4]~reg0 ;
wire \FIFO0_[3] ;
wire \FIFO1_[3] ;
wire \FIFO2_[3] ;
wire \FIFO3_[3] ;
wire \FIFO4_[3] ;
wire \i212~192 ;
wire \VAL[3] ;
wire \i188~3 ;
wire \i212~191 ;
wire \DATA_OUT[3]~reg0 ;
wire \FIFO0_[2] ;
wire \FIFO1_[2] ;
wire \FIFO2_[2] ;
wire \FIFO3_[2] ;
wire \FIFO4_[2] ;
wire \i213~246 ;
wire \VAL[2] ;
wire \i189~3 ;
wire \i213~245 ;
wire \DATA_OUT[2]~reg0 ;
wire \FIFO0_[1] ;
wire \FIFO1_[1] ;
wire \FIFO2_[1] ;
wire \FIFO3_[1] ;
wire \FIFO4_[1] ;
wire \i214~246 ;
wire \VAL[1] ;
wire \i190~3 ;
wire \i214~245 ;
wire \DATA_OUT[1]~reg0 ;
wire \FIFO0_[0] ;
wire \FIFO1_[0] ;
wire \FIFO2_[0] ;
wire \FIFO3_[0] ;
wire \FIFO4_[0] ;
wire \i215~246 ;
wire \VAL[0] ;
wire \i191~3 ;
wire \i215~245 ;
wire \DATA_OUT[0]~reg0 ;


// atom is at Pin_124
flex10ke_io \DATA_VALID_IN~I (
	.datain(),
	.clk(),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\DATA_VALID_IN~dataout ),
	.padio(DATA_VALID_IN));
// synopsys translate_off
defparam \DATA_VALID_IN~I .operation_mode = "input";
defparam \DATA_VALID_IN~I .reg_source_mode = "none";
defparam \DATA_VALID_IN~I .feedback_mode = "from_pin";
// synopsys translate_on

// atom is at Pin_54
flex10ke_io \E_D~I (
	.datain(),
	.clk(),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\E_D~dataout ),
	.padio(E_D));
// synopsys translate_off
defparam \E_D~I .operation_mode = "input";
defparam \E_D~I .reg_source_mode = "none";
defparam \E_D~I .feedback_mode = "from_pin";
// synopsys translate_on