📄 sign_div_unsign_3li.tdf
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--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=4 LPM_PIPELINE=1 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=10 SKIP_BITS=0 aclr clock denominator numerator quotient remainder
--VERSION_BEGIN 6.1 cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ VERSION_END
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION alt_u_div_7qg (aclr, clock, denominator[3..0], numerator[9..0])
RETURNS ( den_out[3..0], quotient[9..0], remainder[3..0]);
--synthesis_resources = lut 50 reg 29
SUBDESIGN sign_div_unsign_3li
(
aclr : input;
clock : input;
denominator[3..0] : input;
numerator[9..0] : input;
quotient[9..0] : output;
remainder[3..0] : output;
)
VARIABLE
divider : alt_u_div_7qg;
adder_result_int[4..0] : WIRE;
adder_cin : WIRE;
adder_dataa[3..0] : WIRE;
adder_datab[3..0] : WIRE;
adder_result[3..0] : WIRE;
gnd_wire : WIRE;
norm_num[9..0] : WIRE;
protect_quotient[9..0] : WIRE;
protect_remainder[3..0] : WIRE;
BEGIN
divider.aclr = aclr;
divider.clock = clock;
divider.denominator[] = denominator[];
divider.numerator[] = norm_num[];
adder_result_int[] = (adder_dataa[], 0) - (adder_datab[], !adder_cin);
adder_result[] = adder_result_int[4..1];
adder_cin = gnd_wire;
adder_dataa[] = divider.den_out[];
adder_datab[] = protect_remainder[];
gnd_wire = B"0";
norm_num[] = numerator[];
protect_quotient[] = divider.quotient[];
protect_remainder[] = divider.remainder[];
quotient[] = protect_quotient[];
remainder[] = protect_remainder[];
END;
--VALID FILE
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