alt_u_div_7qg.tdf

在DE2平台上实现把DVD转换到LED上显示

--alt_u_div DEVICE_FAMILY="Cyclone II" LPM_PIPELINE=1 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=4 WIDTH_N=10 WIDTH_Q=10 WIDTH_R=4 aclr clock den_out denominator numerator quotient remainder
--VERSION_BEGIN 6.1 cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION add_sub_lkc (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_mkc (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);

--synthesis_resources = lut 45 reg 29 
OPTIONS ALTERA_INTERNAL_OPTION = "{-to DFFQuotient[0]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[1]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[2]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[3]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[4]} POWER_UP_LEVEL=HIGH;{-to DFFQuotient[5]} POWER_UP_LEVEL=LOW;{-to DFFQuotient[6]} POWER_UP_LEVEL=LOW;{-to DFFQuotient[7]} POWER_UP_LEVEL=LOW;{-to DFFQuotient[8]} POWER_UP_LEVEL=LOW;{-to DFFQuotient[9]} POWER_UP_LEVEL=LOW;{-to DFFDenominator} POWER_UP_LEVEL=HIGH";

SUBDESIGN alt_u_div_7qg
( 
	aclr	:	input;
	clock	:	input;
	den_out[3..0]	:	output;
	denominator[3..0]	:	input;
	numerator[9..0]	:	input;
	quotient[9..0]	:	output;
	remainder[3..0]	:	output;
) 
VARIABLE 
	DFFDenominator[3..0] : dffe
		WITH (
			power_up = "high"
		);
	DFFNumerator[9..0] : dffe;
	DFFQuotient[9..0] : dffe;
	DFFStage[4..0] : dffe;
	add_sub_0 : add_sub_lkc;
	add_sub_1 : add_sub_mkc;
	add_sub_2_result_int[3..0]	:	WIRE;
	add_sub_2_cout	:	WIRE;
	add_sub_2_dataa[2..0]	:	WIRE;
	add_sub_2_datab[2..0]	:	WIRE;
	add_sub_2_result[2..0]	:	WIRE;
	add_sub_3_result_int[4..0]	:	WIRE;
	add_sub_3_cout	:	WIRE;
	add_sub_3_dataa[3..0]	:	WIRE;
	add_sub_3_datab[3..0]	:	WIRE;
	add_sub_3_result[3..0]	:	WIRE;
	add_sub_4_result_int[5..0]	:	WIRE;
	add_sub_4_cout	:	WIRE;
	add_sub_4_dataa[4..0]	:	WIRE;
	add_sub_4_datab[4..0]	:	WIRE;
	add_sub_4_result[4..0]	:	WIRE;
	add_sub_5_result_int[5..0]	:	WIRE;
	add_sub_5_cout	:	WIRE;
	add_sub_5_dataa[4..0]	:	WIRE;
	add_sub_5_datab[4..0]	:	WIRE;
	add_sub_5_result[4..0]	:	WIRE;
	add_sub_6_result_int[5..0]	:	WIRE;
	add_sub_6_cout	:	WIRE;
	add_sub_6_dataa[4..0]	:	WIRE;
	add_sub_6_datab[4..0]	:	WIRE;
	add_sub_6_result[4..0]	:	WIRE;
	add_sub_7_result_int[5..0]	:	WIRE;
	add_sub_7_cout	:	WIRE;
	add_sub_7_dataa[4..0]	:	WIRE;
	add_sub_7_datab[4..0]	:	WIRE;
	add_sub_7_result[4..0]	:	WIRE;
	add_sub_8_result_int[5..0]	:	WIRE;
	add_sub_8_cout	:	WIRE;
	add_sub_8_dataa[4..0]	:	WIRE;
	add_sub_8_datab[4..0]	:	WIRE;
	add_sub_8_result[4..0]	:	WIRE;
	add_sub_9_result_int[5..0]	:	WIRE;
	add_sub_9_cout	:	WIRE;
	add_sub_9_dataa[4..0]	:	WIRE;
	add_sub_9_datab[4..0]	:	WIRE;
	add_sub_9_result[4..0]	:	WIRE;
	clk_en	: NODE;
	DenominatorIn[54..0]	: WIRE;
	DenominatorIn_tmp[54..0]	: WIRE;
	gnd_wire	: WIRE;
	nose[109..0]	: WIRE;
	NumeratorIn[109..0]	: WIRE;