de2_tv.tan.summary

在DE2平台上实现把DVD转换到LED上显示

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 8.487 ns
From           : DRAM_DQ[13]
To             : Sdram_Control_4Port:u6|mDATAOUT[13]
From Clock     : --
To Clock       : OSC_27
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.751 ns
From           : VGA_Ctrl:u9|H_Cont[10]
To             : VGA_BLANK
From Clock     : OSC_27
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 13.257 ns
From           : DPDT_SW[14]
To             : HEX3[6]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.265 ns
From           : I2C_SDAT
To             : I2C_AV_Config:u1|I2C_Controller:u0|ACK3
From Clock     : --
To Clock       : OSC_50
Failed Paths   : 0

Type           : Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : 0.276 ns
Required Time  : 108.00 MHz ( period = 9.259 ns )
Actual Time    : 111.32 MHz ( period = 8.983 ns )
From           : Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|dffpipe_oe9:ws_brp|dffe5a[1]
To             : Sdram_Control_4Port:u6|mADDR[21]
From Clock     : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'OSC_27'
Slack          : 5.942 ns
Required Time  : 27.00 MHz ( period = 37.037 ns )
Actual Time    : 39.76 MHz ( period = 25.154 ns )
From           : VGA_Ctrl:u9|V_Cont[6]
To             : YUV422_to_444:u7|mCr[7]
From Clock     : OSC_27
To Clock       : OSC_27
Failed Paths   : 0

Type           : Clock Setup: 'OSC_50'
Slack          : 12.802 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 138.93 MHz ( period = 7.198 ns )
From           : I2C_AV_Config:u1|I2C_Controller:u0|SD[22]
To             : I2C_AV_Config:u1|I2C_Controller:u0|SDO
From Clock     : OSC_50
To Clock       : OSC_50
Failed Paths   : 0

Type           : Clock Setup: 'TD_CLK'
Slack          : 17.447 ns
Required Time  : 27.00 MHz ( period = 37.037 ns )
Actual Time    : 51.05 MHz ( period = 19.590 ns )
From           : DIV:u5|lpm_divide:lpm_divide_component|lpm_divide_d6t:auto_generated|sign_div_unsign_3li:divider|alt_u_div_7qg:divider|DFFStage[1]
To             : ITU_656_Decoder:u4|Data_Valid
From Clock     : TD_CLK
To Clock       : TD_CLK
Failed Paths   : 0

Type           : Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2'
Slack          : 49.001 ns
Required Time  : 18.62 MHz ( period = 53.703 ns )
Actual Time    : 212.68 MHz ( period = 4.702 ns )
From           : AUDIO_DAC:u12|LRCK_1X_DIV[3]
To             : AUDIO_DAC:u12|LRCK_1X
From Clock     : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2
To Clock       : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2
Failed Paths   : 0

Type           : Clock Setup: 'TD_HS'
Slack          : N/A
Required Time  : None
Actual Time    : 197.20 MHz ( period = 5.071 ns )
From           : TD_Detect:u2|Stable_Cont[0]
To             : TD_Detect:u2|TD_Stable
From Clock     : TD_HS
To Clock       : TD_HS
Failed Paths   : 0

Type           : Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
Slack          : 0.499 ns
Required Time  : 108.00 MHz ( period = 9.259 ns )
Actual Time    : N/A
From           : Sdram_Control_4Port:u6|command:command1|oe4
To             : Sdram_Control_4Port:u6|command:command1|oe4
From Clock     : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
To Clock       : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2'
Slack          : 0.499 ns
Required Time  : 18.62 MHz ( period = 53.703 ns )
Actual Time    : N/A
From           : AUDIO_DAC:u12|BCK_DIV[1]
To             : AUDIO_DAC:u12|BCK_DIV[1]
From Clock     : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2
To Clock       : Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk2
Failed Paths   : 0

Type           : Clock Hold: 'OSC_50'
Slack          : 0.499 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : I2C_AV_Config:u1|I2C_Controller:u0|SCLK
To             : I2C_AV_Config:u1|I2C_Controller:u0|SCLK
From Clock     : OSC_50
To Clock       : OSC_50
Failed Paths   : 0

Type           : Clock Hold: 'TD_CLK'
Slack          : 0.499 ns
Required Time  : 27.00 MHz ( period = 37.037 ns )
Actual Time    : N/A
From           : ITU_656_Decoder:u4|Start
To             : ITU_656_Decoder:u4|Start
From Clock     : TD_CLK
To Clock       : TD_CLK
Failed Paths   : 0

Type           : Clock Hold: 'OSC_27'
Slack          : 0.499 ns
Required Time  : 27.00 MHz ( period = 37.037 ns )
Actual Time    : N/A
From           : VGA_Ctrl:u9|oVGA_VS
To             : VGA_Ctrl:u9|oVGA_VS
From Clock     : OSC_27
To Clock       : OSC_27
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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