de2_tv.map.rpt

在DE2平台上实现把DVD转换到LED上显示

; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                  ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+----------------------+--------------------------+
; Name                 ; Setting                  ;
+----------------------+--------------------------+
; CYCLONEII_SAFE_WRITE ; "RESTRUCTURE"            ;
+----------------------+--------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                              ;
+-------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------+
; File Name with User-Entered Path          ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                           ;
+-------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------+
; AUDIO_DAC.v                               ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/AUDIO_DAC.v                               ;
; Line_Buffer.v                             ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Line_Buffer.v                             ;
; DIV.v                                     ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/DIV.v                                     ;
; Sdram_Control_4Port/Sdram_RD_FIFO.v       ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Sdram_Control_4Port/Sdram_RD_FIFO.v       ;
; Sdram_Control_4Port/Sdram_WR_FIFO.v       ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Sdram_Control_4Port/Sdram_WR_FIFO.v       ;
; Sdram_Control_4Port/Sdram_Params.h        ; yes             ; User File                    ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Sdram_Control_4Port/Sdram_Params.h        ;
; Sdram_Control_4Port/command.v             ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Sdram_Control_4Port/command.v             ;
; Sdram_Control_4Port/control_interface.v   ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Sdram_Control_4Port/control_interface.v   ;
; Sdram_Control_4Port/sdr_data_path.v       ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Sdram_Control_4Port/sdr_data_path.v       ;
; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Sdram_Control_4Port/Sdram_Control_4Port.v ;
; Sdram_Control_4Port/Sdram_PLL.v           ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Sdram_Control_4Port/Sdram_PLL.v           ;
; MAC_3.v                                   ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/MAC_3.v                                   ;
; Reset_Delay.v                             ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/Reset_Delay.v                             ;
; YCbCr2RGB.v                               ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/YCbCr2RGB.v                               ;
; DE2_TV.v                                  ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/DE2_TV.v                                  ;
; I2C_AV_Config.v                           ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/I2C_AV_Config.v                           ;
; I2C_Controller.v                          ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/I2C_Controller.v                          ;
; SEG7_LUT.v                                ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/SEG7_LUT.v                                ;
; SEG7_LUT_8.v                              ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/SEG7_LUT_8.v                              ;
; YUV422_to_444.v                           ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/YUV422_to_444.v                           ;
; TD_Detect.v                               ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/TD_Detect.v                               ;
; ITU_656_Decoder.v                         ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/ITU_656_Decoder.v                         ;
; VGA_Ctrl.v                                ; yes             ; User Verilog HDL File        ; E:/FPGA-DSP/de2_cd/DE2_demonstrations/DE2_TV/VGA_Ctrl.v                                ;
; lpm_divide.tdf                            ; yes             ; Megafunction                 ; d:/altera/61/quartus/libraries/megafunctions/lpm_divide.tdf                            ;