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📄 de2_tv.map.rpt

📁 在DE2平台上实现把DVD转换到LED上显示
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 77. Source assignments for Line_Buffer:u11|altshift_taps:altshift_taps_component|shift_taps_k0r:auto_generated|altsyncram_q0c1:altsyncram2
 78. Source assignments for I2C_AV_Config:u1|altsyncram:Ram0_rtl_0|altsyncram_kn21:auto_generated
 79. Parameter Settings for User Entity Instance: I2C_AV_Config:u1
 80. Parameter Settings for User Entity Instance: DIV:u5|lpm_divide:lpm_divide_component
 81. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6
 82. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component
 83. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|control_interface:control1
 84. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|command:command1
 85. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|sdr_data_path:data_path1
 86. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component
 87. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component
 88. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component
 89. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component
 90. Parameter Settings for User Entity Instance: YCbCr2RGB:u8|MAC_3:u0|altmult_add:ALTMULT_ADD_component
 91. Parameter Settings for User Entity Instance: YCbCr2RGB:u8|MAC_3:u1|altmult_add:ALTMULT_ADD_component
 92. Parameter Settings for User Entity Instance: YCbCr2RGB:u8|MAC_3:u2|altmult_add:ALTMULT_ADD_component
 93. Parameter Settings for User Entity Instance: VGA_Ctrl:u9
 94. Parameter Settings for User Entity Instance: Line_Buffer:u10|altshift_taps:altshift_taps_component
 95. Parameter Settings for User Entity Instance: Line_Buffer:u11|altshift_taps:altshift_taps_component
 96. Parameter Settings for User Entity Instance: AUDIO_DAC:u12
 97. Parameter Settings for Inferred Entity Instance: I2C_AV_Config:u1|altsyncram:Ram0_rtl_0
 98. dcfifo Parameter Settings by Entity Instance
 99. altmult_add Parameter Settings by Entity Instance
100. altshift_taps Parameter Settings by Entity Instance
101. Analysis & Synthesis Messages
102. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Mon Aug 06 16:55:19 2007   ;
; Quartus II Version                 ; 6.1 Build 201 11/27/2006 SJ Web Edition ;
; Revision Name                      ; DE2_TV                                  ;
; Top-level Entity Name              ; DE2_TV                                  ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 1,231                                   ;
;     Total combinational functions  ; 1,231                                   ;
;     Dedicated logic registers      ; 1,058                                   ;
; Total registers                    ; 1058                                    ;
; Total pins                         ; 426                                     ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 54,208                                  ;
; Embedded Multiplier 9-bit elements ; 18                                      ;
; Total PLLs                         ; 1                                       ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C35F672C8       ;                    ;
; Top-level entity name                                              ; DE2_TV             ; DE2_TV             ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;

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