de2_tv.map.smsg

在DE2平台上实现把DVD转换到LED上显示

Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[7]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[6]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[5]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[4]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[3]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[2]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[1]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[0]"
Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(410): inferring latch(es) for variable "rRD2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[22]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[21]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[20]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[19]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[18]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[17]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[16]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[15]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[14]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[13]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[12]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[11]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[10]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[9]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[8]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[7]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[6]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[5]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[4]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[3]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[2]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[1]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(130): inferred latch for "rRD2_MAX_ADDR[0]"
Info: Elaborating entity "Sdram_PLL" for hierarchy "Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1"
Info: Found 1 design units, including 1 entities, in source file d:/altera/61/quartus/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component"
Info: Elaborated megafunction instantiation "Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component"
Info: Elaborating entity "control_interface" for hierarchy "Sdram_Control_4Port:u6|control_interface:control1"
Warning (10230): Verilog HDL assignment warning at control_interface.v(120): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at control_interface.v(125): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at control_interface.v(150): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "command" for hierarchy "Sdram_Control_4Port:u6|command:command1"
Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable "oe_shift", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[6]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[5]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[4]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[3]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[2]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[1]"
Info (10041): Verilog HDL or VHDL info at command.v(80): inferred latch for "oe_shift[0]"
Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable "oe1", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at command.v(81): inferred latch for "oe1"
Warning (10240): Verilog HDL Always Construct warning at command.v(239): inferring latch(es) for variable "oe2", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at command.v(82): inferred latch for "oe2"
Info: Elaborating entity "sdr_data_path" for hierarchy "Sdram_Control_4Port:u6|sdr_data_path:data_path1"
Warning (10230): Verilog HDL assignment warning at sdr_data_path.v(26): truncated value with size 32 to match size of target (2)
Info: Elaborating entity "Sdram_WR_FIFO" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1"
Info: Found 1 design units, including 1 entities, in source file d:/altera/61/quartus/libraries/megafunctions/dcfifo.tdf
    Info: Found entity 1: dcfifo
Info: Elaborating entity "dcfifo" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component"
Info: Elaborated megafunction instantiation "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component"
Info: Found 1 design units, including 1 entities, in source file db/dcfifo_fnk1.tdf
    Info: Found entity 1: dcfifo_fnk1
Info: Elaborating entity "dcfifo_fnk1" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_kdb.tdf
    Info: Found entity 1: a_gray2bin_kdb
Info: Elaborating entity "a_gray2bin_kdb" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|a_gray2bin_kdb:rdptr_g_gray2bin"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_o96.tdf
    Info: Found entity 1: a_graycounter_o96
Info: Elaborating entity "a_graycounter_o96" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|a_graycounter_o96:rdptr_g1p"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_j27.tdf
    Info: Found entity 1: a_graycounter_j27
Info: Elaborating entity "a_graycounter_j27" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|a_graycounter_j27:wrptr_g1p"
Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_i27.tdf
    Info: Found entity 1: a_graycounter_i27
Info: Elaborating entity "a_graycounter_i27" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|a_graycounter_i27:wrptr_gp"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_jk61.tdf
    Info: Found entity 1: altsyncram_jk61
Info: Elaborating entity "altsyncram_jk61" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|altsyncram_jk61:fifo_ram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_drg1.tdf
    Info: Found entity 1: altsyncram_drg1
Info: Elaborating entity "altsyncram_drg1" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|altsyncram_jk61:fifo_ram|altsyncram_drg1:altsyncram3"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf
    Info: Found entity 1: dffpipe_oe9
Info: Elaborating entity "dffpipe_oe9" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|dffpipe_oe9:rs_brp"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_vd8.tdf
    Info: Found entity 1: alt_synch_pipe_vd8
Info: Elaborating entity "alt_synch_pipe_vd8" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf
    Info: Found entity 1: dffpipe_pe9
Info: Elaborating entity "dffpipe_pe9" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe6"
Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_0e8.tdf
    Info: Found entity 1: alt_synch_pipe_0e8
Info: Elaborating entity "alt_synch_pipe_0e8" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf
    Info: Found entity 1: dffpipe_qe9
Info: Elaborating entity "dffpipe_qe9" for hierarchy "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_fnk1:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe9"
Info: Elaborating entity "Sdram_RD_FIFO" for hierarchy "Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1"
Info: Elaborating entity "YUV422_to_444" for hierarchy "YUV422_to_444:u7"
Info: Elaborating entity "YCbCr2RGB" for hierarchy "YCbCr2RGB:u8"
Warning (10230): Verilog HDL assignment warning at YCbCr2RGB.v(111): truncated value with size 32 to match size of target (20)
Warning (10230): Verilog HDL assignment warning at YCbCr2RGB.v(112): truncated value with size 32 to match size of target (20)
Warning (10230): Verilog HDL assignment warning at YCbCr2RGB.v(113): truncated value with size 32 to match size of target (20)
Info: Elaborating entity "MAC_3" for hierarchy "YCbCr2RGB:u8|MAC_3:u0"
Info: Found 1 design units, including 1 entities, in source file d:/altera/61/quartus/libraries/megafunctions/altmult_add.tdf
    Info: Found entity 1: altmult_add
Info: Elaborating entity "altmult_add" for hierarchy "YCbCr2RGB:u8|MAC_3:u0|altmult_add:ALTMULT_ADD_component"
Info: Elaborated megafunction instantiation "YCbCr2RGB:u8|MAC_3:u0|altmult_add:ALTMULT_ADD_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_add_4f74.tdf
    Info: Found entity 1: mult_add_4f74
Info: Elaborating entity "mult_add_4f74" for hierarchy "YCbCr2RGB:u8|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/ded_mult_ob91.tdf
    Info: Found entity 1: ded_mult_ob91
Info: Elaborating entity "ded_mult_ob91" for hierarchy "YCbCr2RGB:u8|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult1"
Info: Found 1 design units, including 1 entities, in source file db/dffpipe_b3c.tdf
    Info: Found entity 1: dffpipe_b3c
Info: Elaborating entity "dffpipe_b3c" for hierarchy "YCbCr2RGB:u8|MAC_3:u0|altmult_add:ALTMULT_ADD_component|mult_add_4f74:auto_generated|ded_mult_ob91:ded_mult1|dffpipe_b3c:pre_result"
Info: Elaborating entity "VGA_Ctrl" for hierarchy "VGA_Ctrl:u9"
Warning (10230): Verilog HDL assignment warning at VGA_Ctrl.v(67): truncated value with size 32 to match size of target (22)