de2_tv.map.smsg

在DE2平台上实现把DVD转换到LED上显示

Warning (10034): Output port "LCD_BLON" at DE2_TV.v(249) has no driver
Warning (10034): Output port "LCD_RW" at DE2_TV.v(250) has no driver
Warning (10034): Output port "LCD_EN" at DE2_TV.v(251) has no driver
Warning (10034): Output port "LCD_RS" at DE2_TV.v(252) has no driver
Warning (10034): Output port "SD_CLK" at DE2_TV.v(257) has no driver
Warning (10034): Output port "TDO" at DE2_TV.v(268) has no driver
Warning (10034): Output port "ENET_CMD" at DE2_TV.v(280) has no driver
Warning (10034): Output port "ENET_CS_N" at DE2_TV.v(281) has no driver
Warning (10034): Output port "ENET_WR_N" at DE2_TV.v(282) has no driver
Warning (10034): Output port "ENET_RD_N" at DE2_TV.v(283) has no driver
Warning (10034): Output port "ENET_RST_N" at DE2_TV.v(284) has no driver
Warning (10034): Output port "ENET_CLK" at DE2_TV.v(286) has no driver
Info: Elaborating entity "SEG7_LUT_8" for hierarchy "SEG7_LUT_8:u0"
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT_8:u0|SEG7_LUT:u0"
Info: Elaborating entity "I2C_AV_Config" for hierarchy "I2C_AV_Config:u1"
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(55): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at I2C_AV_Config.v(106): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "I2C_Controller" for hierarchy "I2C_AV_Config:u1|I2C_Controller:u0"
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(78): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(77): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at I2C_Controller.v(90): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "TD_Detect" for hierarchy "TD_Detect:u2"
Info: Elaborating entity "Reset_Delay" for hierarchy "Reset_Delay:u3"
Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(22): truncated value with size 32 to match size of target (22)
Info: Elaborating entity "ITU_656_Decoder" for hierarchy "ITU_656_Decoder:u4"
Warning (10230): Verilog HDL assignment warning at ITU_656_Decoder.v(44): truncated value with size 18 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at ITU_656_Decoder.v(124): truncated value with size 32 to match size of target (10)
Info: Elaborating entity "DIV" for hierarchy "DIV:u5"
Info: Found 1 design units, including 1 entities, in source file d:/altera/61/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborating entity "lpm_divide" for hierarchy "DIV:u5|lpm_divide:lpm_divide_component"
Info: Elaborated megafunction instantiation "DIV:u5|lpm_divide:lpm_divide_component"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_d6t.tdf
    Info: Found entity 1: lpm_divide_d6t
Info: Elaborating entity "lpm_divide_d6t" for hierarchy "DIV:u5|lpm_divide:lpm_divide_component|lpm_divide_d6t:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_3li.tdf
    Info: Found entity 1: sign_div_unsign_3li
Info: Elaborating entity "sign_div_unsign_3li" for hierarchy "DIV:u5|lpm_divide:lpm_divide_component|lpm_divide_d6t:auto_generated|sign_div_unsign_3li:divider"
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_7qg.tdf
    Info: Found entity 1: alt_u_div_7qg
Info: Elaborating entity "alt_u_div_7qg" for hierarchy "DIV:u5|lpm_divide:lpm_divide_component|lpm_divide_d6t:auto_generated|sign_div_unsign_3li:divider|alt_u_div_7qg:divider"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
    Info: Found entity 1: add_sub_lkc
Info: Elaborating entity "add_sub_lkc" for hierarchy "DIV:u5|lpm_divide:lpm_divide_component|lpm_divide_d6t:auto_generated|sign_div_unsign_3li:divider|alt_u_div_7qg:divider|add_sub_lkc:add_sub_0"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
    Info: Found entity 1: add_sub_mkc
Info: Elaborating entity "add_sub_mkc" for hierarchy "DIV:u5|lpm_divide:lpm_divide_component|lpm_divide_d6t:auto_generated|sign_div_unsign_3li:divider|alt_u_div_7qg:divider|add_sub_mkc:add_sub_1"
Info: Elaborating entity "Sdram_Control_4Port" for hierarchy "Sdram_Control_4Port:u6"
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(372): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(415): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(417): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(418): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(419): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(420): truncated value with size 32 to match size of target (23)
Warning (10230): Verilog HDL assignment warning at Sdram_Control_4Port.v(421): truncated value with size 32 to match size of target (23)
Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(410): inferring latch(es) for variable "rWR1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[22]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[21]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[20]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[19]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[18]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[17]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[16]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[15]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[14]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[13]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[12]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[11]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[10]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[9]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[8]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[7]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[6]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[5]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[4]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[3]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[2]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[1]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(121): inferred latch for "rWR1_MAX_ADDR[0]"
Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(410): inferring latch(es) for variable "rWR2_MAX_ADDR", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[22]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[21]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[20]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[19]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[18]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[17]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[16]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[15]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[14]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[13]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[12]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[11]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[10]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[9]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[8]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[7]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[6]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[5]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[4]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[3]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[2]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[1]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(124): inferred latch for "rWR2_MAX_ADDR[0]"
Warning (10240): Verilog HDL Always Construct warning at Sdram_Control_4Port.v(410): inferring latch(es) for variable "rRD1_MAX_ADDR", which holds its previous value in one or more paths through the always construct
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[22]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[21]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[20]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[19]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[18]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[17]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[16]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[15]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[14]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[13]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[12]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[11]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[10]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[9]"
Info (10041): Verilog HDL or VHDL info at Sdram_Control_4Port.v(127): inferred latch for "rRD1_MAX_ADDR[8]"