prev_cmp_first_press.map.qmsg

我EDA课程设计做的用VHDL 写的智能电子密码锁

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 15 20:52:30 2007 " "Info: Processing started: Sun Jul 15 20:52:30 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FIRST_PRESS -c FIRST_PRESS " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FIRST_PRESS -c FIRST_PRESS" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIRST_PRESS.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FIRST_PRESS.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FIRST_PRESS-ONE " "Info: Found design unit 1: FIRST_PRESS-ONE" {  } { { "FIRST_PRESS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/FIRST_PRESS/FIRST_PRESS.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 FIRST_PRESS " "Info: Found entity 1: FIRST_PRESS" {  } { { "FIRST_PRESS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/FIRST_PRESS/FIRST_PRESS.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FIRST_PRESS " "Info: Elaborating entity \"FIRST_PRESS\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RST FIRST_PRESS.vhd(15) " "Warning (10492): VHDL Process Statement warning at FIRST_PRESS.vhd(15): signal \"RST\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "FIRST_PRESS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/FIRST_PRESS/FIRST_PRESS.vhd" 15 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_MULTIPLE_SIGNALS_IN_EVENT_EXPR" "FIRST_PRESS.vhd(16) " "Error (10397): VHDL Event Expression error at FIRST_PRESS.vhd(16): can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S" {  } { { "FIRST_PRESS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/FIRST_PRESS/FIRST_PRESS.vhd" 16 0 0 } }  } 0 10397 "VHDL Event Expression error at %1!s!: can't form clock edge from S'EVENT by combining it with an expression that depends on a signal besides S" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_OPERATOR_CALL_FAILED" "\"or\" FIRST_PRESS.vhd(16) " "Error (10658): VHDL Operator error at FIRST_PRESS.vhd(16): failed to evaluate call to operator \"\"or\"\"" {  } { { "FIRST_PRESS.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/FIRST_PRESS/FIRST_PRESS.vhd" 16 0 0 } }  } 0 10658 "VHDL Operator error at %2!s!: failed to evaluate call to operator \"%1!s!\"" 0 0 "" 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun Jul 15 20:52:33 2007 " "Error: Processing ended: Sun Jul 15 20:52:33 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}