first_press.tan.qmsg

我EDA课程设计做的用VHDL 写的智能电子密码锁

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "RST " "Info: Assuming node \"RST\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 7 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "KEY_CNT " "Info: Detected ripple clock \"KEY_CNT\" as buffer" {  } { { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 13 -1 0 } } { "e:/vhdl/eda/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/vhdl/eda/quartus/bin/Assignment Editor.qase" 1 { { 0 "KEY_CNT" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_TSU_RESULT" "KEY_BUFF\[2\] KEY_IN\[2\] RST 3.500 ns register " "Info: tsu for register \"KEY_BUFF\[2\]\" (data pin = \"KEY_IN\[2\]\", clock pin = \"RST\") is 3.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest pin register " "Info: + Longest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns KEY_IN\[2\] 1 PIN PIN_54 2 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 2; PIN Node = 'KEY_IN\[2\]'" {  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY_IN[2] } "NODE_NAME" } } { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 3.800 ns KEY_BUFF\[2\] 2 REG LC1_D14 1 " "Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC1_D14; Fanout = 1; REG Node = 'KEY_BUFF\[2\]'" {  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { KEY_IN[2] KEY_BUFF[2] } "NODE_NAME" } } { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 94.74 % ) " "Info: Total cell delay = 3.600 ns ( 94.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 5.26 % ) " "Info: Total interconnect delay = 0.200 ns ( 5.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { KEY_IN[2] KEY_BUFF[2] } "NODE_NAME" } } { "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "3.800 ns" { KEY_IN[2] KEY_IN[2]~out KEY_BUFF[2] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.300 ns + " "Info: + Micro setup delay of destination is 3.300 ns" {  } { { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RST destination 3.600 ns - Shortest register " "Info: - Shortest clock path from clock \"RST\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns RST 1 CLK PIN_126 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 6; CLK Node = 'RST'" {  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { RST } "NODE_NAME" } } { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 3.600 ns KEY_BUFF\[2\] 2 REG LC1_D14 1 " "Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC1_D14; Fanout = 1; REG Node = 'KEY_BUFF\[2\]'" {  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { RST KEY_BUFF[2] } "NODE_NAME" } } { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 94.44 % ) " "Info: Total cell delay = 3.400 ns ( 94.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 5.56 % ) " "Info: Total interconnect delay = 0.200 ns ( 5.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { RST KEY_BUFF[2] } "NODE_NAME" } } { "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { RST RST~out KEY_BUFF[2] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { KEY_IN[2] KEY_BUFF[2] } "NODE_NAME" } } { "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "3.800 ns" { KEY_IN[2] KEY_IN[2]~out KEY_BUFF[2] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.600ns } "" } } { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { RST KEY_BUFF[2] } "NODE_NAME" } } { "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { RST RST~out KEY_BUFF[2] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.400ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "KEY_BUFF\[2\] KEY_IN\[2\] RST -0.200 ns register " "Info: th for register \"KEY_BUFF\[2\]\" (data pin = \"KEY_IN\[2\]\", clock pin = \"RST\") is -0.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "RST destination 3.600 ns + Longest register " "Info: + Longest clock path from clock \"RST\" to destination register is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns RST 1 CLK PIN_126 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 6; CLK Node = 'RST'" {  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { RST } "NODE_NAME" } } { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 3.600 ns KEY_BUFF\[2\] 2 REG LC1_D14 1 " "Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC1_D14; Fanout = 1; REG Node = 'KEY_BUFF\[2\]'" {  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { RST KEY_BUFF[2] } "NODE_NAME" } } { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 94.44 % ) " "Info: Total cell delay = 3.400 ns ( 94.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 5.56 % ) " "Info: Total interconnect delay = 0.200 ns ( 5.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { RST KEY_BUFF[2] } "NODE_NAME" } } { "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { RST RST~out KEY_BUFF[2] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.400ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns KEY_IN\[2\] 1 PIN PIN_54 2 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 2; PIN Node = 'KEY_IN\[2\]'" {  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY_IN[2] } "NODE_NAME" } } { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 3.800 ns KEY_BUFF\[2\] 2 REG LC1_D14 1 " "Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC1_D14; Fanout = 1; REG Node = 'KEY_BUFF\[2\]'" {  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { KEY_IN[2] KEY_BUFF[2] } "NODE_NAME" } } { "FIRST_PRESS.vhd" "" { Text "E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 94.74 % ) " "Info: Total cell delay = 3.600 ns ( 94.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns ( 5.26 % ) " "Info: Total interconnect delay = 0.200 ns ( 5.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { KEY_IN[2] KEY_BUFF[2] } "NODE_NAME" } } { "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "3.800 ns" { KEY_IN[2] KEY_IN[2]~out KEY_BUFF[2] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { RST KEY_BUFF[2] } "NODE_NAME" } } { "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "3.600 ns" { RST RST~out KEY_BUFF[2] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.400ns } "" } } { "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/vhdl/eda/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { KEY_IN[2] KEY_BUFF[2] } "NODE_NAME" } } { "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/vhdl/eda/quartus/bin/Technology_Viewer.qrui" "3.800 ns" { KEY_IN[2] KEY_IN[2]~out KEY_BUFF[2] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 2.000ns 1.600ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 9 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 16 09:29:57 2007 " "Info: Processing ended: Fri Feb 16 09:29:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}