first_press.hier_info

我EDA课程设计做的用VHDL 写的智能电子密码锁

|FIRST_PRESS
KEY_IN[0] => Equal0.IN3
KEY_IN[0] => KEY_BUFF[0].DATAIN
KEY_IN[1] => KEY_BUFF[1].DATAIN
KEY_IN[1] => Equal0.IN2
KEY_IN[2] => KEY_BUFF[2].DATAIN
KEY_IN[2] => Equal0.IN1
KEY_IN[3] => KEY_BUFF[3].DATAIN
KEY_IN[3] => Equal0.IN0
CLK => ~NO_FANOUT~
RST => KEY_BUFF[1].LATCH_ENABLE
RST => KEY_BUFF[2].LATCH_ENABLE
RST => KEY_BUFF[3].LATCH_ENABLE
RST => KEY_BUFF[0].LATCH_ENABLE
RST => KEY_CNT.ACLR
RST => TOUT$latch.ACLR
TOUT <= TOUT$latch.DB_MAX_OUTPUT_PORT_TYPE