bijiaoqi.tan.qmsg

我EDA课程设计做的用VHDL 写的智能电子密码锁

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 15 20:11:02 2007 " "Info: Processing started: Sun Jul 15 20:11:02 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off BIJIAOQI -c BIJIAOQI " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off BIJIAOQI -c BIJIAOQI" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "OPEN_LOCK\$latch " "Warning: Node \"OPEN_LOCK\$latch\" is a latch" {  } { { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "ZS " "Info: Assuming node \"ZS\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 9 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "EN " "Info: Assuming node \"EN\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 8 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}