count_20s.hier_info

我EDA课程设计做的用VHDL 写的智能电子密码锁

|COUNT_20S
CLK => COUNT[14].CLK
CLK => COUNT[13].CLK
CLK => COUNT[12].CLK
CLK => COUNT[11].CLK
CLK => COUNT[10].CLK
CLK => COUNT[9].CLK
CLK => COUNT[8].CLK
CLK => COUNT[7].CLK
CLK => COUNT[6].CLK
CLK => COUNT[5].CLK
CLK => COUNT[4].CLK
CLK => COUNT[3].CLK
CLK => COUNT[2].CLK
CLK => COUNT[1].CLK
CLK => COUNT[0].CLK
CLK => SPK.CLK
CLK => ZS_OUT~reg0.CLK
BJ_IN => ZS_OUT~1.OUTPUTSELECT
BJ_IN => COUNT~29.OUTPUTSELECT
BJ_IN => COUNT~28.OUTPUTSELECT
BJ_IN => COUNT~27.OUTPUTSELECT
BJ_IN => COUNT~26.OUTPUTSELECT
BJ_IN => COUNT~25.OUTPUTSELECT
BJ_IN => COUNT~24.OUTPUTSELECT
BJ_IN => COUNT~23.OUTPUTSELECT
BJ_IN => COUNT~22.OUTPUTSELECT
BJ_IN => COUNT~21.OUTPUTSELECT
BJ_IN => COUNT~20.OUTPUTSELECT
BJ_IN => COUNT~19.OUTPUTSELECT
BJ_IN => COUNT~18.OUTPUTSELECT
BJ_IN => COUNT~17.OUTPUTSELECT
BJ_IN => COUNT~16.OUTPUTSELECT
BJ_IN => COUNT~15.OUTPUTSELECT
BJ_IN => SPK.ENA
SPEAK <= SPK.DB_MAX_OUTPUT_PORT_TYPE
ZS_OUT <= ZS_OUT~reg0.DB_MAX_OUTPUT_PORT_TYPE