count_20s.tan.qmsg

我EDA课程设计做的用VHDL 写的智能电子密码锁

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 7 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[14\] 106.38 MHz 9.4 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 106.38 MHz between source register \"lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[14\]\" (period= 9.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.300 ns + Longest register register " "Info: + Longest register to register delay is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC5_D1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D1; Fanout = 3; REG Node = 'lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 2.000 ns Equal0~135 2 COMB LC1_D1 1 " "Info: 2: + IC(0.300 ns) + CELL(1.700 ns) = 2.000 ns; Loc. = LC1_D1; Fanout = 1; COMB Node = 'Equal0~135'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] Equal0~135 } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 4.300 ns Equal0~136 3 COMB LC4_D2 1 " "Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC4_D2; Fanout = 1; COMB Node = 'Equal0~136'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { Equal0~135 Equal0~136 } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 6.200 ns Equal0~137 4 COMB LC1_D2 19 " "Info: 4: + IC(0.300 ns) + CELL(1.600 ns) = 6.200 ns; Loc. = LC1_D2; Fanout = 19; COMB Node = 'Equal0~137'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Equal0~136 Equal0~137 } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.100 ns) 8.300 ns lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[14\] 5 REG LC8_D3 2 " "Info: 5: + IC(1.000 ns) + CELL(1.100 ns) = 8.300 ns; Loc. = LC8_D3; Fanout = 2; REG Node = 'lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[14\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { Equal0~137 lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns ( 69.88 % ) " "Info: Total cell delay = 5.800 ns ( 69.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 30.12 % ) " "Info: Total interconnect delay = 2.500 ns ( 30.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] Equal0~135 Equal0~136 Equal0~137 lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] Equal0~135 Equal0~136 Equal0~137 lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } { 0.000ns 0.300ns 0.900ns 0.300ns 1.000ns } { 0.000ns 1.700ns 1.400ns 1.600ns 1.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[14\] 2 REG LC8_D3 2 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_D3; Fanout = 2; REG Node = 'lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[14\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC5_D1 3 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_D1; Fanout = 3; REG Node = 'lpm_counter:COUNT_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.300 ns" { lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] Equal0~135 Equal0~136 Equal0~137 lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.300 ns" { lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] Equal0~135 Equal0~136 Equal0~137 lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } { 0.000ns 0.300ns 0.900ns 0.300ns 1.000ns } { 0.000ns 1.700ns 1.400ns 1.600ns 1.100ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[14] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "SPK BJ_IN CLK 1.300 ns register " "Info: tsu for register \"SPK\" (data pin = \"BJ_IN\", clock pin = \"CLK\") is 1.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.100 ns + Longest pin register " "Info: + Longest pin to register delay is 3.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns BJ_IN 1 PIN PIN_126 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 17; PIN Node = 'BJ_IN'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { BJ_IN } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.000 ns) 3.100 ns SPK 2 REG LC6_D4 2 " "Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 3.100 ns; Loc. = LC6_D4; Fanout = 2; REG Node = 'SPK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.100 ns" { BJ_IN SPK } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 96.77 % ) " "Info: Total cell delay = 3.000 ns ( 96.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns ( 3.23 % ) " "Info: Total interconnect delay = 0.100 ns ( 3.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { BJ_IN SPK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { BJ_IN BJ_IN~out SPK } { 0.000ns 0.000ns 0.100ns } { 0.000ns 2.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK 1 CLK PIN_55 17 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 17; CLK Node = 'CLK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns SPK 2 REG LC6_D4 2 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_D4; Fanout = 2; REG Node = 'SPK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { CLK SPK } "NODE_NAME" } } { "COUNT_20S.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/COUNT_20S/COUNT_20S.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK SPK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out SPK } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { BJ_IN SPK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.100 ns" { BJ_IN BJ_IN~out SPK } { 0.000ns 0.000ns 0.100ns } { 0.000ns 2.000ns 1.000ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { CLK SPK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { CLK CLK~out SPK } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}