90bbc934dbad001a1837b42d837911b3

FPGA中针对Biss通讯协议解码VHDL语言源码

/* system.h
 *
 * Machine generated for a CPU named "cpu" as defined in:
 * C:\altera\biss_01_03\small_cpu.ptf
 *
 * Generated: 2006-03-07 13:57:43.093
 *
 */
#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "small_cpu"
#define ALT_CPU_NAME "cpu"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "CYCLONE"
#define DBC1C12
#define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDERR "/dev/jtag_uart"
#define ALT_CPU_FREQ 75000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "small"

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x01000020
#define NIOS2_RESET_ADDR 0x01000000

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_UART
#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_SYSID

/*
 * jtag_uart configuration
 *
 */

#define JTAG_UART_NAME "/dev/jtag_uart"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x00000800
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 0
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0

/*
 * uart1 configuration
 *
 */

#define UART1_NAME "/dev/uart1"
#define UART1_TYPE "altera_avalon_uart"
#define UART1_BASE 0x00000820
#define UART1_SPAN 32
#define UART1_IRQ 1
#define UART1_BAUD 115200
#define UART1_DATA_BITS 8
#define UART1_FIXED_BAUD 1
#define UART1_PARITY 'N'
#define UART1_STOP_BITS 1
#define UART1_USE_CTS_RTS 0
#define UART1_USE_EOP_REGISTER 0
#define UART1_SIM_TRUE_BAUD 0
#define UART1_SIM_CHAR_STREAM ""
#define UART1_FREQ 75000000

/*
 * uart2 configuration
 *
 */

#define UART2_NAME "/dev/uart2"
#define UART2_TYPE "altera_avalon_uart"
#define UART2_BASE 0x00000840
#define UART2_SPAN 32
#define UART2_IRQ 2
#define UART2_BAUD 115200
#define UART2_DATA_BITS 8
#define UART2_FIXED_BAUD 1
#define UART2_PARITY 'N'
#define UART2_STOP_BITS 1
#define UART2_USE_CTS_RTS 0
#define UART2_USE_EOP_REGISTER 0
#define UART2_SIM_TRUE_BAUD 0
#define UART2_SIM_CHAR_STREAM ""
#define UART2_FREQ 75000000

/*
 * epcs_controller configuration
 *
 */

#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"
#define EPCS_CONTROLLER_BASE 0x00001000
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_IRQ 3
#define EPCS_CONTROLLER_DATABITS 8
#define EPCS_CONTROLLER_TARGETCLOCK 20
#define EPCS_CONTROLLER_CLOCKUNITS "MHz"
#define EPCS_CONTROLLER_CLOCKMULT 1000000
#define EPCS_CONTROLLER_NUMSLAVES 1
#define EPCS_CONTROLLER_ISMASTER 1
#define EPCS_CONTROLLER_CLOCKPOLARITY 0
#define EPCS_CONTROLLER_CLOCKPHASE 0
#define EPCS_CONTROLLER_LSBFIRST 0
#define EPCS_CONTROLLER_EXTRADELAY 1
#define EPCS_CONTROLLER_TARGETSSDELAY 100
#define EPCS_CONTROLLER_DELAYUNITS "us"
#define EPCS_CONTROLLER_DELAYMULT "1e-006"
#define EPCS_CONTROLLER_PREFIX "epcs_"
#define EPCS_CONTROLLER_REGISTER_OFFSET 0x200
#define EPCS_CONTROLLER_CLOCKUNIT "kHz"
#define EPCS_CONTROLLER_DELAYUNIT "us"

/*
 * cfi_flash configuration
 *
 */

#define CFI_FLASH_NAME "/dev/cfi_flash"
#define CFI_FLASH_TYPE "altera_avalon_cfi_flash"
#define CFI_FLASH_BASE 0x00800000
#define CFI_FLASH_SPAN 8388608
#define CFI_FLASH_SETUP_VALUE 40
#define CFI_FLASH_WAIT_VALUE 160
#define CFI_FLASH_HOLD_VALUE 40
#define CFI_FLASH_TIMING_UNITS "ns"
#define CFI_FLASH_UNIT_MULTIPLIER 1
#define CFI_FLASH_SIZE 8388608

/*
 * led configuration
 *
 */

#define LED_NAME "/dev/led"
#define LED_TYPE "altera_avalon_pio"
#define LED_BASE 0x00000810
#define LED_SPAN 16
#define LED_DO_TEST_BENCH_WIRING 0
#define LED_DRIVEN_SIM_VALUE 0x0000
#define LED_HAS_TRI 0
#define LED_HAS_OUT 1
#define LED_HAS_IN 0
#define LED_CAPTURE 0
#define LED_EDGE_TYPE "NONE"
#define LED_IRQ_TYPE "NONE"
#define LED_FREQ 75000000

/*
 * sdram configuration
 *
 */

#define SDRAM_NAME "/dev/sdram"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x01000000
#define SDRAM_SPAN 16777216
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 1
#define SDRAM_SDRAM_DATA_WIDTH 32
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 100
#define SDRAM_CAS_LATENCY 3
#define SDRAM_T_RFC 70
#define SDRAM_T_RP 20
#define SDRAM_T_MRD 3
#define SDRAM_T_RCD 20
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 14
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0
#define SDRAM_SHARED_DATA 0
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_IS_INITIALIZED 1
#define SDRAM_SDRAM_BANK_WIDTH 2

/*
 * flash_bus configuration
 *
 */

#define FLASH_BUS_NAME "/dev/flash_bus"
#define FLASH_BUS_TYPE "altera_avalon_tri_state_bridge"

/*
 * PIO_lm74 configuration
 *
 */

#define PIO_LM74_NAME "/dev/PIO_lm74"
#define PIO_LM74_TYPE "altera_avalon_pio"
#define PIO_LM74_BASE 0x00000870
#define PIO_LM74_SPAN 16
#define PIO_LM74_DO_TEST_BENCH_WIRING 0
#define PIO_LM74_DRIVEN_SIM_VALUE 0x0000
#define PIO_LM74_HAS_TRI 1
#define PIO_LM74_HAS_OUT 0
#define PIO_LM74_HAS_IN 0
#define PIO_LM74_CAPTURE 0
#define PIO_LM74_EDGE_TYPE "NONE"
#define PIO_LM74_IRQ_TYPE "NONE"
#define PIO_LM74_FREQ 75000000

/*
 * sysid configuration
 *
 */

#define SYSID_NAME "/dev/sysid"
#define SYSID_TYPE "altera_avalon_sysid"
#define SYSID_BASE 0x00000808
#define SYSID_SPAN 8
#define SYSID_ID 1793001889u
#define SYSID_TIMESTAMP 1141734295u

/*
 * Positionsdaten configuration
 *
 */

#define POSITIONSDATEN_NAME "/dev/Positionsdaten"
#define POSITIONSDATEN_TYPE "altera_avalon_pio"
#define POSITIONSDATEN_BASE 0x000008C0
#define POSITIONSDATEN_SPAN 16
#define POSITIONSDATEN_DO_TEST_BENCH_WIRING 0
#define POSITIONSDATEN_DRIVEN_SIM_VALUE 0x0000
#define POSITIONSDATEN_HAS_TRI 0
#define POSITIONSDATEN_HAS_OUT 0
#define POSITIONSDATEN_HAS_IN 1
#define POSITIONSDATEN_CAPTURE 1
#define POSITIONSDATEN_EDGE_TYPE "RISING"
#define POSITIONSDATEN_IRQ_TYPE "NONE"
#define POSITIONSDATEN_FREQ 75000000

/*
 * Steuerbits configuration
 *
 */

#define STEUERBITS_NAME "/dev/Steuerbits"
#define STEUERBITS_TYPE "altera_avalon_pio"
#define STEUERBITS_BASE 0x000008B0
#define STEUERBITS_SPAN 16
#define STEUERBITS_DO_TEST_BENCH_WIRING 0
#define STEUERBITS_DRIVEN_SIM_VALUE 0x0000
#define STEUERBITS_HAS_TRI 0
#define STEUERBITS_HAS_OUT 0
#define STEUERBITS_HAS_IN 1
#define STEUERBITS_CAPTURE 1
#define STEUERBITS_EDGE_TYPE "RISING"
#define STEUERBITS_IRQ_TYPE "NONE"
#define STEUERBITS_FREQ 75000000

/*
 * MODUS configuration
 *
 */

#define MODUS_NAME "/dev/MODUS"
#define MODUS_TYPE "altera_avalon_pio"
#define MODUS_BASE 0x00000900
#define MODUS_SPAN 16
#define MODUS_DO_TEST_BENCH_WIRING 0
#define MODUS_DRIVEN_SIM_VALUE 0x0000
#define MODUS_HAS_TRI 0
#define MODUS_HAS_OUT 1
#define MODUS_HAS_IN 0
#define MODUS_CAPTURE 0
#define MODUS_EDGE_TYPE "NONE"
#define MODUS_IRQ_TYPE "NONE"
#define MODUS_FREQ 75000000

/*
 * button configuration
 *
 */

#define BUTTON_NAME "/dev/button"
#define BUTTON_TYPE "altera_avalon_pio"
#define BUTTON_BASE 0x00000860
#define BUTTON_SPAN 16
#define BUTTON_IRQ 4
#define BUTTON_DO_TEST_BENCH_WIRING 0
#define BUTTON_DRIVEN_SIM_VALUE 0x0000
#define BUTTON_HAS_TRI 0
#define BUTTON_HAS_OUT 0
#define BUTTON_HAS_IN 1
#define BUTTON_CAPTURE 1
#define BUTTON_EDGE_TYPE "RISING"
#define BUTTON_IRQ_TYPE "LEVEL"
#define BUTTON_FREQ 75000000

/*
 * IDundADRundWNR configuration
 *
 */

#define IDUNDADRUNDWNR_NAME "/dev/IDundADRundWNR"
#define IDUNDADRUNDWNR_TYPE "altera_avalon_pio"
#define IDUNDADRUNDWNR_BASE 0x00000880
#define IDUNDADRUNDWNR_SPAN 16
#define IDUNDADRUNDWNR_DO_TEST_BENCH_WIRING 0
#define IDUNDADRUNDWNR_DRIVEN_SIM_VALUE 0x0000
#define IDUNDADRUNDWNR_HAS_TRI 0
#define IDUNDADRUNDWNR_HAS_OUT 1
#define IDUNDADRUNDWNR_HAS_IN 0
#define IDUNDADRUNDWNR_CAPTURE 0
#define IDUNDADRUNDWNR_EDGE_TYPE "NONE"
#define IDUNDADRUNDWNR_IRQ_TYPE "NONE"
#define IDUNDADRUNDWNR_FREQ 75000000

/*
 * DataWrite configuration
 *
 */

#define DATAWRITE_NAME "/dev/DataWrite"
#define DATAWRITE_TYPE "altera_avalon_pio"
#define DATAWRITE_BASE 0x000008A0
#define DATAWRITE_SPAN 16
#define DATAWRITE_DO_TEST_BENCH_WIRING 0
#define DATAWRITE_DRIVEN_SIM_VALUE 0x0000
#define DATAWRITE_HAS_TRI 0
#define DATAWRITE_HAS_OUT 1
#define DATAWRITE_HAS_IN 0
#define DATAWRITE_CAPTURE 0
#define DATAWRITE_EDGE_TYPE "NONE"
#define DATAWRITE_IRQ_TYPE "NONE"
#define DATAWRITE_FREQ 75000000

/*
 * DataRead configuration
 *
 */

#define DATAREAD_NAME "/dev/DataRead"
#define DATAREAD_TYPE "altera_avalon_pio"
#define DATAREAD_BASE 0x000008D0
#define DATAREAD_SPAN 16
#define DATAREAD_DO_TEST_BENCH_WIRING 0
#define DATAREAD_DRIVEN_SIM_VALUE 0x0000
#define DATAREAD_HAS_TRI 0
#define DATAREAD_HAS_OUT 0
#define DATAREAD_HAS_IN 1
#define DATAREAD_CAPTURE 1
#define DATAREAD_EDGE_TYPE "RISING"
#define DATAREAD_IRQ_TYPE "NONE"
#define DATAREAD_FREQ 75000000

/*
 * MCD configuration
 *
 */

#define MCD_NAME "/dev/MCD"
#define MCD_TYPE "altera_avalon_pio"
#define MCD_BASE 0x00000930
#define MCD_SPAN 16
#define MCD_DO_TEST_BENCH_WIRING 0
#define MCD_DRIVEN_SIM_VALUE 0x0000
#define MCD_HAS_TRI 0
#define MCD_HAS_OUT 0
#define MCD_HAS_IN 1
#define MCD_CAPTURE 1
#define MCD_EDGE_TYPE "RISING"
#define MCD_IRQ_TYPE "NONE"
#define MCD_FREQ 75000000

/*
 * length configuration
 *
 */

#define LENGTH_NAME "/dev/length"
#define LENGTH_TYPE "altera_avalon_pio"
#define LENGTH_BASE 0x00000890
#define LENGTH_SPAN 16
#define LENGTH_DO_TEST_BENCH_WIRING 0
#define LENGTH_DRIVEN_SIM_VALUE 0x0000
#define LENGTH_HAS_TRI 0
#define LENGTH_HAS_OUT 1
#define LENGTH_HAS_IN 0
#define LENGTH_CAPTURE 0
#define LENGTH_EDGE_TYPE "NONE"
#define LENGTH_IRQ_TYPE "NONE"
#define LENGTH_FREQ 75000000

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK none
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      SDRAM

/*
 * The text section is initialised so no bootloader will be required.
 * Set a variable to tell crt0.S to provide code at the reset address and
 * to initialise rwdata if appropriate.
 */

#define ALT_NO_BOOTLOADER


#endif /* __SYSTEM_H_ */