i2c_altera.fit.eqn

程序实现的功能是通过I2C配置SAA7113芯片,然后通过逻辑分析仪器查看芯片的输出数据 可以通过视频口输出视频 redlogic的程序

D1L41 = D1_t6_qfbk # D1_y3;

--D1_t6 is I2C:inst1|t6 at LC_X38_Y9_N8
--operation mode is normal

D1_t6 = DFFEAS(D1L41, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , LB1_Deglitch, D1_t5, , , VCC);


--D1L51 is I2C:inst1|Cmd_reg[2]~51 at LC_X37_Y9_N9
--operation mode is normal

D1L51 = D1L2 # LB1_Deglitch & (D1L41 # D1_s1a);


--G1_cnt[15] is filter:inst8|cnt[15] at LC_X38_Y11_N7
--operation mode is normal

G1_cnt[15]_carry_eqn = (!G1L73 & G1L24) # (G1L73 & G1L34);
G1_cnt[15]_lut_out = G1_cnt[15] $ (G1_cnt[15]_carry_eqn);
G1_cnt[15] = DFFEAS(G1_cnt[15]_lut_out, GLOBAL(SYSCLK), VCC, , , , , , );


--MB1_safe_q[4] is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|safe_q[4] at LC_X37_Y11_N4
--operation mode is normal

MB1_safe_q[4]_lut_out = MB1_safe_q[4] $ !MB1L11;
MB1_safe_q[4] = DFFEAS(MB1_safe_q[4]_lut_out, GLOBAL(PB1__clk0), VCC, , , , , LB1L1, );


--MB1_safe_q[3] is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|safe_q[3] at LC_X37_Y11_N3
--operation mode is arithmetic

MB1_safe_q[3]_lut_out = MB1_safe_q[3] $ MB1L8;
MB1_safe_q[3] = DFFEAS(MB1_safe_q[3]_lut_out, GLOBAL(PB1__clk0), VCC, , , , , LB1L1, );

--MB1L11 is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|counter_cella3~COUT at LC_X37_Y11_N3
--operation mode is arithmetic

MB1L11_cout_0 = !MB1L8 # !MB1_safe_q[3];
MB1L11 = CARRY(MB1L11_cout_0);

--MB1L21 is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|counter_cella3~COUTCOUT1_4 at LC_X37_Y11_N3
--operation mode is arithmetic

MB1L21_cout_1 = !MB1L9 # !MB1_safe_q[3];
MB1L21 = CARRY(MB1L21_cout_1);


--GB71L2 is I2C:inst1|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~38 at LC_X37_Y11_N9
--operation mode is normal

GB71L2 = MB1_safe_q[4] & MB1_safe_q[3];


--MB1_safe_q[1] is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|safe_q[1] at LC_X37_Y11_N1
--operation mode is arithmetic

MB1_safe_q[1]_lut_out = MB1_safe_q[1] $ (MB1L2);
MB1_safe_q[1] = DFFEAS(MB1_safe_q[1]_lut_out, GLOBAL(PB1__clk0), VCC, , , , , LB1L1, );

--MB1L5 is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|counter_cella1~COUT at LC_X37_Y11_N1
--operation mode is arithmetic

MB1L5_cout_0 = !MB1L2 # !MB1_safe_q[1];
MB1L5 = CARRY(MB1L5_cout_0);

--MB1L6 is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|counter_cella1~COUTCOUT1_2 at LC_X37_Y11_N1
--operation mode is arithmetic

MB1L6_cout_1 = !MB1L3 # !MB1_safe_q[1];
MB1L6 = CARRY(MB1L6_cout_1);


--MB1_safe_q[2] is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|safe_q[2] at LC_X37_Y11_N2
--operation mode is arithmetic

MB1_safe_q[2]_lut_out = MB1_safe_q[2] $ (!MB1L5);
MB1_safe_q[2] = DFFEAS(MB1_safe_q[2]_lut_out, GLOBAL(PB1__clk0), VCC, , , , , LB1L1, );

--MB1L8 is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|counter_cella2~COUT at LC_X37_Y11_N2
--operation mode is arithmetic

MB1L8_cout_0 = MB1_safe_q[2] & (!MB1L5);
MB1L8 = CARRY(MB1L8_cout_0);

--MB1L9 is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|counter_cella2~COUTCOUT1_4 at LC_X37_Y11_N2
--operation mode is arithmetic

MB1L9_cout_1 = MB1_safe_q[2] & (!MB1L6);
MB1L9 = CARRY(MB1L9_cout_1);


--MB1_safe_q[0] is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|safe_q[0] at LC_X37_Y11_N0
--operation mode is arithmetic

MB1_safe_q[0]_lut_out = !MB1_safe_q[0];
MB1_safe_q[0] = DFFEAS(MB1_safe_q[0]_lut_out, GLOBAL(PB1__clk0), VCC, , , , , LB1L1, );

--MB1L2 is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|counter_cella0~COUT at LC_X37_Y11_N0
--operation mode is arithmetic

MB1L2_cout_0 = MB1_safe_q[0];
MB1L2 = CARRY(MB1L2_cout_0);

--MB1L3 is I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|counter_cella0~COUTCOUT1_5 at LC_X37_Y11_N0
--operation mode is arithmetic

MB1L3_cout_1 = MB1_safe_q[0];
MB1L3 = CARRY(MB1L3_cout_1);


--GB71L1 is I2C:inst1|div_by_n:div_by_x|lpm_compare:$00002|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 at LC_X37_Y11_N7
--operation mode is normal

GB71L1 = GB71L2 & !MB1_safe_q[0] & !MB1_safe_q[2] & !MB1_safe_q[1];

--LB1_Deglitch is I2C:inst1|div_by_n:div_by_x|Deglitch at LC_X37_Y11_N7
--operation mode is normal

LB1_Deglitch = DFFEAS(GB71L1, GLOBAL(PB1__clk0), VCC, , , , , , );


--D1_s1 is I2C:inst1|s1 at LC_X38_Y9_N7
--operation mode is normal

D1_s1_lut_out = D1_s3 # !D1_Ss_idle & D1_Cmd_reg[1] & !D1_Start_condition;
D1_s1 = DFFEAS(D1_s1_lut_out, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , LB1_Deglitch, , , , );


--D1_t1a is I2C:inst1|t1a at LC_X37_Y10_N8
--operation mode is normal

D1_t1a_lut_out = GND;
D1_t1a = DFFEAS(D1_t1a_lut_out, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , LB1_Deglitch, D1_t1, , , VCC);


--D1_t4a is I2C:inst1|t4a at LC_X37_Y10_N9
--operation mode is normal

D1_t4a_lut_out = GND;
D1_t4a = DFFEAS(D1_t4a_lut_out, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , LB1_Deglitch, D1_t4, , , VCC);


--D1L24 is I2C:inst1|Start_condition~39 at LC_X38_Y9_N5
--operation mode is normal

D1_y3_qfbk = D1_y3;
D1L24 = LB1_Deglitch & (D1_y3_qfbk # D1_Cmd_reg[1] & !D1_Ss_idle);

--D1_y3 is I2C:inst1|y3 at LC_X38_Y9_N5
--operation mode is normal

D1_y3 = DFFEAS(D1L24, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , LB1_Deglitch, D1_y2, , , VCC);


--C1_cmd_start is i2c_cmd:inst|cmd_start at LC_X35_Y10_N8
--operation mode is normal

C1_cmd_start_lut_out = C1_STATE.GEN_S # C1_cmd_start & !C1_STATE.S_WAIT;
C1_cmd_start = DFFEAS(C1_cmd_start_lut_out, GLOBAL(PB1__clk0), VCC, , , , , !G1_rst_out, );


--C1_cmd_send is i2c_cmd:inst|cmd_send at LC_X36_Y10_N5
--operation mode is normal

C1_cmd_send_lut_out = C1_STATE.SUBADDR # C1L41 # C1_STATE.DATA;
C1_cmd_send = DFFEAS(C1_cmd_send_lut_out, GLOBAL(PB1__clk0), VCC, , , , , !G1_rst_out, );


--D1_BitCnt[2] is I2C:inst1|BitCnt[2] at LC_X39_Y10_N2
--operation mode is normal

D1_BitCnt[2]_lut_out = !D1_BitCnt[2];
D1_BitCnt[2] = DFFEAS(D1_BitCnt[2]_lut_out, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , D1L9, , , , );


--D1_BitCnt[1] is I2C:inst1|BitCnt[1] at LC_X39_Y10_N4
--operation mode is normal

D1_BitCnt[1]_lut_out = !D1_BitCnt[1];
D1_BitCnt[1] = DFFEAS(D1_BitCnt[1]_lut_out, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , D1L6, , , , );


--D1_BitCnt[0] is I2C:inst1|BitCnt[0] at LC_X37_Y10_N7
--operation mode is normal

D1_BitCnt[0]_lut_out = !D1_BitCnt[0];
D1_BitCnt[0] = DFFEAS(D1_BitCnt[0]_lut_out, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , D1L8, , , , );


--C1_i2c_data_t[7] is i2c_cmd:inst|i2c_data_t[7] at LC_X35_Y11_N5
--operation mode is normal

C1_i2c_data_t[7]_lut_out = NB1_q_a[7] & (C1_STATE.DATA # C1L55 & C1_i2c_data_t[7]) # !NB1_q_a[7] & C1L55 & (C1_i2c_data_t[7]);
C1_i2c_data_t[7] = DFFEAS(C1_i2c_data_t[7]_lut_out, GLOBAL(PB1__clk0), VCC, , , , , !G1_rst_out, );


--D1_Sh_reg[6] is I2C:inst1|Sh_reg[6] at LC_X36_Y10_N9
--operation mode is normal

D1_Sh_reg[6]_lut_out = D1L2 & (C1_i2c_data_t[6] # D1_t2 & D1_Sh_reg[5]) # !D1L2 & D1_t2 & (D1_Sh_reg[5]);
D1_Sh_reg[6] = DFFEAS(D1_Sh_reg[6]_lut_out, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , D1L93, , , , );


--D1L93 is I2C:inst1|Sh_reg[7]~8 at LC_X37_Y10_N6
--operation mode is normal

D1L93 = D1_x1 & D1_t2 & LB1_Deglitch # !D1_x1 & (C1_execute # D1_t2 & LB1_Deglitch);


--D1L44 is I2C:inst1|t0~85 at LC_X38_Y10_N2
--operation mode is normal

D1L44 = D1_t2 & (!D1_BitCnt[1] # !D1_BitCnt[2] # !D1_BitCnt[0]);


--D1_s2a is I2C:inst1|s2a at LC_X38_Y10_N1
--operation mode is normal

D1_s2a_lut_out = D1_s2;
D1_s2a = DFFEAS(D1_s2a_lut_out, GLOBAL(PB1__clk0), GLOBAL(G1_rst_out), , LB1_Deglitch, , , , );


--L2_WORD_SR[3] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] at LC_X14_Y14_N2
--operation mode is normal

L2_WORD_SR[3] = AMPP_FUNCTION(A1L5, L2_word_counter[0], L2_word_counter[1], altera_internal_jtag, L2L13, !L1_clear_signal, SB1_state[4], H1L4);


--BB31_match_out is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_mbpmg:\trigger_in_trigger_module_enabled_gen:trigger_in_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|match_out at LC_X23_Y11_N3
--operation mode is normal

BB31_match_out = AMPP_FUNCTION(PCLK, Q3_dffs[19], BB9_holdff, B1_acq_trigger_in_reg[8], BB31L2, VCC);


--Y1L1 is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|process0~19 at LC_X24_Y11_N2
--operation mode is normal

Y1L1 = AMPP_FUNCTION(N1_is_buffer_wrapped_once, Q3_dffs[5]);

--Y1_trigger_happened_ff[0] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_level_seq_mgr:ela_level_seq_mgr|trigger_happened_ff[0] at LC_X24_Y11_N2
--operation mode is normal

Y1_trigger_happened_ff[0] = AMPP_FUNCTION(PCLK, BB31_match_out, QB1_Q[1], GND, Y1L1);


--Q4_dffs[33] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[33] at LC_X15_Y12_N6
--operation mode is normal

Q4_dffs[33] = AMPP_FUNCTION(A1L5, Q4_dffs[34], !B1_reset_all, M1_trigger_setup_ena);


--Q4_dffs[34] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[34] at LC_X15_Y12_N0
--operation mode is normal

Q4_dffs[34] = AMPP_FUNCTION(A1L5, Q4_dffs[35], !B1_reset_all, M1_trigger_setup_ena);


--BB21_holdff is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1|holdff at LC_X15_Y13_N8
--operation mode is normal

BB21_holdff = AMPP_FUNCTION(PCLK, B1_acq_trigger_in_reg[11], VCC);


--Q4_dffs[35] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[35] at LC_X14_Y12_N2
--operation mode is normal

Q4_dffs[35] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !B1_reset_all, M1_trigger_setup_ena);


--Q4_dffs[0] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[0] at LC_X18_Y16_N8
--operation mode is normal

Q4_dffs[0] = AMPP_FUNCTION(A1L5, Q4_dffs[1], !B1_reset_all, M1_trigger_setup_ena);


--Q4_dffs[1] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[1] at LC_X18_Y16_N0
--operation mode is normal

Q4_dffs[1] = AMPP_FUNCTION(A1L5, Q4_dffs[2], !B1_reset_all, M1_trigger_setup_ena);


--BB1_holdff is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1|holdff at LC_X18_Y16_N9
--operation mode is normal

BB1_holdff = AMPP_FUNCTION(PCLK, B1_acq_trigger_in_reg[0], VCC, GND);


--Q4_dffs[2] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[2] at LC_X18_Y16_N6
--operation mode is normal

Q4_dffs[2] = AMPP_FUNCTION(A1L5, Q4_dffs[3], !B1_reset_all, M1_trigger_setup_ena);


--Q4_dffs[3] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[3] at LC_X18_Y16_N3
--operation mode is normal

Q4_dffs[3] = AMPP_FUNCTION(A1L5, Q4_dffs[4], !B1_reset_all, GND, M1_trigger_setup_ena);


--Q4_dffs[4] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[4] at LC_X18_Y16_N7
--operation mode is normal

Q4_dffs[4] = AMPP_FUNCTION(A1L5, Q4_dffs[5], !B1_reset_all, M1_trigger_setup_ena);


--BB2_holdff is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1|holdff at LC_X18_Y15_N5
--operation mode is normal

BB2_holdff = AMPP_FUNCTION(PCLK, B1_acq_trigger_in_reg[1], VCC, GND);


--Q4_dffs[5] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[5] at LC_X15_Y15_N6
--operation mode is normal

Q4_dffs[5] = AMPP_FUNCTION(A1L5, Q4_dffs[6], !B1_reset_all, M1_trigger_setup_ena);


--Q4_dffs[6] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[6] at LC_X15_Y15_N5
--operation mode is normal

Q4_dffs[6] = AMPP_FUNCTION(A1L5, Q4_dffs[7], !B1_reset_all, GND, M1_trigger_setup_ena);


--Q4_dffs[7] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[7] at LC_X15_Y15_N9
--operation mode is normal

Q4_dffs[7] = AMPP_FUNCTION(A1L5, Q4_dffs[8], !B1_reset_all, M1_trigger_setup_ena);


--BB3_holdff is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\g