i2c_altera.tan.rpt

程序实现的功能是通过I2C配置SAA7113芯片,然后通过逻辑分析仪器查看芯片的输出数据 可以通过视频口输出视频 redlogic的程序

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Type                                                   ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                                                                                                              ; To                                                                                                             ; From Clock                              ; To Clock                                ; Failed Paths ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Worst-case tsu                                         ; N/A       ; None                             ; 11.826 ns                        ; SCL                                                                                                                                                                                                                                                               ; I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|safe_q[3]                              ;                                         ; SYSCLK                                  ; 0            ;
; Worst-case tco                                         ; N/A       ; None                             ; 7.749 ns                         ; I2C:inst1|SCL_reg                                                                                                                                                                                                                                                 ; SCL                                                                                                            ; SYSCLK                                  ;                                         ; 0            ;
; Worst-case tpd                                         ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                                                                          ; altera_reserved_tdo                                                                                            ;                                         ;                                         ; 0            ;
; Worst-case th                                          ; N/A       ; None                             ; 3.554 ns                         ; altera_internal_jtag                                                                                                                                                                                                                                              ; sld_signaltap:auto_signaltap_0|bypass_reg_out                                                                  ;                                         ; altera_internal_jtag~TCKUTAP            ; 0            ;
; Clock Setup: 'SYSCLK'                                  ; 1.090 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; i2c_cmd:inst|rom_addr[5]                                                                                                                                                                                                                                          ; SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_hsu:auto_generated|ram_block1a7~porta_address_reg5    ; PLL:inst3|altpll:altpll_component|_clk0 ; SYSCLK                                  ; 0            ;
; Clock Setup: 'PLL:inst3|altpll:altpll_component|_clk0' ; 12.031 ns ; 16.67 MHz ( period = 60.000 ns ) ; N/A                              ; filter:inst8|rst_out                                                                                                                                                                                                                                              ; i2c_cmd:inst|rom_addr[0]                                                                                       ; SYSCLK                                  ; PLL:inst3|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'            ; N/A       ; None                             ; 83.93 MHz ( period = 11.914 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]                                                                                                                                                                                                                ; sld_hub:sld_hub_inst|hub_tdo                                                                                   ; altera_internal_jtag~TCKUTAP            ; altera_internal_jtag~TCKUTAP            ; 0            ;
; Clock Setup: 'PCLK'                                    ; N/A       ; None                             ; 117.63 MHz ( period = 8.501 ns ) ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|match_out ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable ; PCLK                                    ; PCLK                                    ; 0            ;
; Clock Hold: 'PLL:inst3|altpll:altpll_component|_clk0'  ; 0.822 ns  ; 16.67 MHz ( period = 60.000 ns ) ; N/A                              ; i2c_cmd:inst|execute                                                                                                                                                                                                                                              ; i2c_cmd:inst|execute                                                                                           ; PLL:inst3|altpll:altpll_component|_clk0 ; PLL:inst3|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'SYSCLK'                                   ; 1.314 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; filter:inst8|cnt[12]                                                                                                                                                                                                                                              ; filter:inst8|cnt[12]                                                                                           ; SYSCLK                                  ; SYSCLK                                  ; 0            ;
; Total number of failed paths                           ;           ;                                  ;                                  ;                                                                                                                                                                                                                                                                   ;                                                                                                                ;                                         ;                                         ; 0            ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;