i2c_altera.tan.summary

程序实现的功能是通过I2C配置SAA7113芯片,然后通过逻辑分析仪器查看芯片的输出数据 可以通过视频口输出视频 redlogic的程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 11.826 ns
From           : SCL
To             : I2C:inst1|div_by_n:div_by_x|lpm_counter:counter|cntr_986:auto_generated|safe_q[3]
From Clock     : 
To Clock       : SYSCLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.749 ns
From           : I2C:inst1|SCL_reg
To             : SCL
From Clock     : SYSCLK
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.554 ns
From           : altera_internal_jtag
To             : sld_signaltap:auto_signaltap_0|bypass_reg_out
From Clock     : 
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'SYSCLK'
Slack          : 1.090 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : i2c_cmd:inst|rom_addr[5]
To             : SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_hsu:auto_generated|ram_block1a7~porta_address_reg5
From Clock     : PLL:inst3|altpll:altpll_component|_clk0
To Clock       : SYSCLK
Failed Paths   : 0

Type           : Clock Setup: 'PLL:inst3|altpll:altpll_component|_clk0'
Slack          : 12.031 ns
Required Time  : 16.67 MHz ( period = 60.000 ns )
Actual Time    : N/A
From           : filter:inst8|rst_out
To             : i2c_cmd:inst|rom_addr[0]
From Clock     : SYSCLK
To Clock       : PLL:inst3|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 83.93 MHz ( period = 11.914 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'PCLK'
Slack          : N/A
Required Time  : None
Actual Time    : 117.63 MHz ( period = 8.501 ns )
From           : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1|match_out
To             : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable
From Clock     : PCLK
To Clock       : PCLK
Failed Paths   : 0

Type           : Clock Hold: 'PLL:inst3|altpll:altpll_component|_clk0'
Slack          : 0.822 ns
Required Time  : 16.67 MHz ( period = 60.000 ns )
Actual Time    : N/A
From           : i2c_cmd:inst|execute
To             : i2c_cmd:inst|execute
From Clock     : PLL:inst3|altpll:altpll_component|_clk0
To Clock       : PLL:inst3|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'SYSCLK'
Slack          : 1.314 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : filter:inst8|cnt[12]
To             : filter:inst8|cnt[12]
From Clock     : SYSCLK
To Clock       : SYSCLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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