i2c_altera.eda.rpt

来自「程序实现的功能是通过I2C配置SAA7113芯片,然后通过逻辑分析仪器查看芯片的」· RPT 代码 · 共 89 行

EDA Netlist Writer report for I2C_ALTERA
Sat Oct 15 11:41:57 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Tool Settings
  4. Simulation Tool Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sat Oct 15 11:41:56 2005 ;
; Revision Name             ; I2C_ALTERA                            ;
; Top-level Entity Name     ; I2C_ALTERA                            ;
; Family                    ; Cyclone                               ;
; Simulation Tool Writer    ; Successful                            ;
+---------------------------+---------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Simulation Tool Settings                                                                             ;
+------------------------------------------------------+-----------------------------------------------+
; Option                                               ; Setting                                       ;
+------------------------------------------------------+-----------------------------------------------+
; Tool Name                                            ; ModelSim (Verilog HDL output from Quartus II) ;
; Generate Netlist for Functional Simulation Only      ; Off                                           ;
; Time scale                                           ; 1 ps                                          ;
; Truncate long hierarchy paths                        ; Off                                           ;
; Map illegal HDL characters                           ; Off                                           ;
; Flatten buses into individual nodes                  ; Off                                           ;
; Maintain hierarchy                                   ; Off                                           ;
; Bring out device-wide set/reset signals as ports     ; Off                                           ;
; Output Excalibur stripe as a single module or entity ; Off                                           ;
; Enable glitch filtering                              ; Off                                           ;
+------------------------------------------------------+-----------------------------------------------+


+-----------------------------------------------------------------------------------+
; Simulation Tool Generated Files                                                   ;
+-----------------------------------------------------------------------------------+
; Generated Files                                                                   ;
+-----------------------------------------------------------------------------------+
; D:/RedLogic/RCII_samples/VideoCap_RCE02/Proj/simulation/modelsim/I2C_ALTERA.vo    ;
; D:/RedLogic/RCII_samples/VideoCap_RCE02/Proj/simulation/modelsim/I2C_ALTERA_v.sdo ;
+-----------------------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Oct 15 11:41:54 2005
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off I2C_ALTERA -c I2C_ALTERA
Info: Generated files "I2C_ALTERA.vo" and "I2C_ALTERA_v.sdo" in directory "D:/RedLogic/RCII_samples/VideoCap_RCE02/Proj/simulation/modelsim/" for EDA simulation tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Oct 15 11:41:56 2005
    Info: Elapsed time: 00:00:03