📄 ps2_keyboard_interface.map.rpt
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; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |ps2_keyboard|uart_if:inst3|data_out[7]~reg0 ;
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |ps2_keyboard|ps2_keyboard_interface:inst|rx_ascii[6] ;
; 4:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |ps2_keyboard|uart_if:inst3|uart:U1|txmit:u2|tsr[5] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------+
+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: ps2_keyboard_interface:inst ;
+-----------------------------+-------+------------------------------------+
; Parameter Name ; Value ; Type ;
+-----------------------------+-------+------------------------------------+
; TIMER_60USEC_VALUE_PP ; 2950 ; Untyped ;
; TIMER_60USEC_BITS_PP ; 12 ; Untyped ;
; TIMER_5USEC_VALUE_PP ; 186 ; Untyped ;
; TIMER_5USEC_BITS_PP ; 8 ; Untyped ;
; TRAP_SHIFT_KEYS_PP ; 0 ; Untyped ;
; m1_rx_clk_h ; 1 ; Untyped ;
; m1_rx_clk_l ; 0 ; Untyped ;
; m1_rx_falling_edge_marker ; 13 ; Untyped ;
; m1_rx_rising_edge_marker ; 14 ; Untyped ;
; m1_tx_force_clk_l ; 3 ; Untyped ;
; m1_tx_first_wait_clk_h ; 10 ; Untyped ;
; m1_tx_first_wait_clk_l ; 11 ; Untyped ;
; m1_tx_reset_timer ; 12 ; Untyped ;
; m1_tx_wait_clk_h ; 2 ; Untyped ;
; m1_tx_clk_h ; 4 ; Untyped ;
; m1_tx_clk_l ; 5 ; Untyped ;
; m1_tx_wait_keyboard_ack ; 6 ; Untyped ;
; m1_tx_done_recovery ; 7 ; Untyped ;
; m1_tx_error_no_keyboard_ack ; 8 ; Untyped ;
; m1_tx_rising_edge_marker ; 9 ; Untyped ;
; m2_rx_data_ready ; 1 ; Untyped ;
; m2_rx_data_ready_ack ; 0 ; Untyped ;
+-----------------------------+-------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/CycloneNios/S7_PS2_RS232/Proj/ps2_keyboard_interface.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Mon Oct 09 10:56:35 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off KEYBAORD -c ps2_keyboard_interface
Info: Found 1 design units, including 1 entities, in source file ../src/ref2/div_4.v
Info: Found entity 1: div_4
Warning: (10273) Verilog HDL warning at rcvr.v(50): extended using "x" or "z"
Warning: (10268) Verilog HDL information at rcvr.v(97): Always Construct contains both blocking and non-blocking assignments
Info: Found 1 design units, including 1 entities, in source file ../src/ref2/rcvr.v
Info: Found entity 1: rcvr
Info: Found 1 design units, including 1 entities, in source file ../src/ref2/txmit.v
Info: Found entity 1: txmit
Info: Found 1 design units, including 1 entities, in source file ../src/ref2/uart.v
Info: Found entity 1: uart
Info: Found 1 design units, including 1 entities, in source file ../src/ref2/uart_if.v
Info: Found entity 1: uart_if
Info: Found 1 design units, including 1 entities, in source file div_256.v
Info: Found entity 1: div_256
Info: Found 1 design units, including 1 entities, in source file ps2_keyboard.bdf
Info: Found entity 1: ps2_keyboard
Info: Found 1 design units, including 1 entities, in source file ../Src/ref2/ps2_keyboard.v
Info: Found entity 1: ps2_keyboard_interface
Info: Found 1 design units, including 1 entities, in source file data_buf.v
Info: Found entity 1: data_buf
Info: Elaborating entity "ps2_keyboard" for the top level hierarchy
Warning: Port "tx_write" of type ps2_keyboard_interface and instance "inst" is missing source signal
Warning: Port "tx_data" of type ps2_keyboard_interface and instance "inst" is missing source signal
Warning: Port "rxd" of type uart_if and instance "inst3" is missing source signal
Info: Elaborating entity "uart_if" for hierarchy "uart_if:inst3"
Warning: Verilog HDL assignment warning at uart_if.v(49): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at uart_if.v(51): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at uart_if.v(61): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at uart_if.v(62): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at uart_if.v(63): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at uart_if.v(64): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(69): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(70): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at uart_if.v(71): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at uart_if.v(72): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(78): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(82): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(85): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at uart_if.v(91): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(101): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(102): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(103): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(108): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(114): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(125): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(130): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at uart_if.v(135): truncated value with size 32 to match size of target (1)
Info: Elaborating entity "uart" for hierarchy "uart_if:inst3|uart:U1"
Info: Elaborating entity "rcvr" for hierarchy "uart_if:inst3|uart:U1|rcvr:u1"
Warning: Verilog HDL assignment warning at rcvr.v(92): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at rcvr.v(134): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "txmit" for hierarchy "uart_if:inst3|uart:U1|txmit:u2"
Warning: Verilog HDL assignment warning at txmit.v(86): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at txmit.v(147): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "div_4" for hierarchy "div_4:inst2"
Warning: Verilog HDL assignment warning at div_4.v(8): truncated value with size 32 to match size of target (13)
Info: Elaborating entity "ps2_keyboard_interface" for hierarchy "ps2_keyboard_interface:inst"
Info: (10035) Verilog HDL or VHDL information at ps2_keyboard.v(211): object "shift_key_on" declared but not used
Warning: Verilog HDL assignment warning at ps2_keyboard.v(283): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(284): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(285): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(286): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(287): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(293): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(301): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(307): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(314): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(322): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at ps2_keyboard.v(328): truncated value with size 32 to match size of target (1)
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