ps2_keyboard_interface.tan.rpt

本实验实现PS/2接口与RS-232接口的数据传输

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; mclk            ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'mclk'                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                         ; To                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------+---------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 58.77 MHz ( period = 17.016 ns )                    ; uart_if:inst3|uart:U1|txmit:u2|tbr[6]                        ; uart_if:inst3|uart:U1|txmit:u2|tsr[6]       ; mclk       ; mclk     ; None                        ; None                      ; 2.345 ns                ;
; N/A                                     ; 60.98 MHz ( period = 16.398 ns )                    ; uart_if:inst3|uart:U1|txmit:u2|tbr[1]                        ; uart_if:inst3|uart:U1|txmit:u2|tsr[1]       ; mclk       ; mclk     ; None                        ; None                      ; 2.036 ns                ;
; N/A                                     ; 61.09 MHz ( period = 16.368 ns )                    ; uart_if:inst3|uart:U1|txmit:u2|tbr[2]                        ; uart_if:inst3|uart:U1|txmit:u2|tsr[2]       ; mclk       ; mclk     ; None                        ; None                      ; 2.021 ns                ;
; N/A                                     ; 61.15 MHz ( period = 16.352 ns )                    ; uart_if:inst3|uart:U1|txmit:u2|tbr[5]                        ; uart_if:inst3|uart:U1|txmit:u2|tsr[5]       ; mclk       ; mclk     ; None                        ; None                      ; 2.013 ns                ;
; N/A                                     ; 61.29 MHz ( period = 16.316 ns )                    ; uart_if:inst3|uart:U1|txmit:u2|tbr[0]                        ; uart_if:inst3|uart:U1|txmit:u2|tsr[0]       ; mclk       ; mclk     ; None                        ; None                      ; 1.995 ns                ;
; N/A                                     ; 62.35 MHz ( period = 16.038 ns )                    ; uart_if:inst3|uart:U1|txmit:u2|tbr[3]                        ; uart_if:inst3|uart:U1|txmit:u2|tsr[3]       ; mclk       ; mclk     ; None                        ; None                      ; 1.856 ns                ;
; N/A                                     ; 62.85 MHz ( period = 15.910 ns )                    ; uart_if:inst3|uart:U1|txmit:u2|tbr[4]                        ; uart_if:inst3|uart:U1|txmit:u2|tsr[4]       ; mclk       ; mclk     ; None                        ; None                      ; 1.792 ns                ;
; N/A                                     ; 84.62 MHz ( period = 11.818 ns )                    ; ps2_keyboard_interface:inst|q[5]                             ; ps2_keyboard_interface:inst|rx_ascii[2]     ; mclk       ; mclk     ; None                        ; None                      ; 11.557 ns               ;
; N/A                                     ; 84.84 MHz ( period = 11.787 ns )                    ; ps2_keyboard_interface:inst|q[1]                             ; ps2_keyboard_interface:inst|rx_ascii[2]     ; mclk       ; mclk     ; None                        ; None                      ; 11.499 ns               ;
; N/A                                     ; 85.81 MHz ( period = 11.654 ns )                    ; ps2_keyboard_interface:inst|q[8]                             ; ps2_keyboard_interface:inst|rx_ascii[2]     ; mclk       ; mclk     ; None                        ; None                      ; 11.393 ns               ;
; N/A                                     ; 85.87 MHz ( period = 11.646 ns )                    ; ps2_keyboard_interface:inst|q[5]                             ; ps2_keyboard_interface:inst|rx_ascii[6]     ; mclk       ; mclk     ; None                        ; None                      ; 11.383 ns               ;
; N/A                                     ; 86.01 MHz ( period = 11.627 ns )                    ; ps2_keyboard_interface:inst|right_shift_key                  ; ps2_keyboard_interface:inst|rx_ascii[2]     ; mclk       ; mclk     ; None                        ; None                      ; 11.339 ns               ;
; N/A                                     ; 86.09 MHz ( period = 11.616 ns )                    ; ps2_keyboard_interface:inst|q[1]                             ; ps2_keyboard_interface:inst|rx_ascii[6]     ; mclk       ; mclk     ; None                        ; None                      ; 11.326 ns               ;
; N/A                                     ; 86.17 MHz ( period = 11.605 ns )                    ; ps2_keyboard_interface:inst|left_shift_key                   ; ps2_keyboard_interface:inst|rx_ascii[2]     ; mclk       ; mclk     ; None                        ; None                      ; 11.317 ns               ;
; N/A                                     ; 86.70 MHz ( period = 11.534 ns )                    ; ps2_keyboard_interface:inst|q[6]                             ; ps2_keyboard_interface:inst|rx_ascii[2]     ; mclk       ; mclk     ; None                        ; None                      ; 11.273 ns               ;