data_buf.v

来自「本实验实现PS/2接口与RS-232接口的数据传输」· Verilog 代码 · 共 26 行

module data_buf(data_in,data_in_buf,clk1_8m,reset);
input [7:0] data_in;
input clk1_8m;
input reset;
output [7:0] data_in_buf;

reg [7:0] data_in_buf;
reg [3:0] i;

always @ (posedge clk1_8m or negedge reset)
if (!reset)
begin
data_in_buf<=data_in;
i<=0;
end
else if(i<4'b1110)
begin
data_in_buf<=data_in_buf;
i<=i+1;
end
else
begin
data_in_buf<=8'bzzzz_zzzz;
i<=4'b1110;
end
endmodule