vpr_types.h

用于学术研究的FPGA布局布线软件VPR

#ifndef SPEC
#define DEBUG 1			/* Echoes input & checks error conditions */
		    /* Only causes about a 1% speed degradation in V 3.10 */
#endif

/*#define CREATE_ECHO_FILES*//* prints echo files */
/*#define PRINT_SINK_DELAYS*//*prints the sink delays to files */
/*#define PRINT_NET_SLACKS*//*prints out all slacks in the circuit */
/*#define PRINT_PLACE_CRIT_PATH*//*prints out placement estimated critical path */
/*#define PRINT_NET_DELAYS*//*prints out delays for all connections */
/*#define PRINT_TIMING_GRAPH*//*prints out the timing graph */
/*#define PRINT_REL_POS_DISTR *//*prints out the relative distribution graph for placements */

#ifdef SPEC
#define NO_GRAPHICS		/* Rips out graphics (for non-X11 systems)      */
#define NDEBUG			/* Turns off assertion checking for extra speed */
#endif

#define TOKENS " \t\n"		/* Input file parsing. */
/*#define VERBOSE 1*//* Prints all sorts of intermediate data */

enum e_pin_type
{ OPEN = -1, DRIVER = 0, RECEIVER = 1 };

/* Pin is unconnected, driving a net or in the fanout, respectively. */

enum e_side
{ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3 };

typedef size_t bitfield;

#define MINOR 0			/* For update_screen.  Denotes importance of update. */
#define MAJOR 1

#define HUGE_FLOAT 1.e30

/* Want to avoid overflows of shorts.  OPINs can have edges to 4 * width if  *
 * they are on all 4 sides, so set MAX_CHANNEL_WIDTH to 8000.                */

#define MAX_CHANNEL_WIDTH 8000
#define MAX_SHORT 32767

#define EMPTY -1

enum sched_type
{ AUTO_SCHED, USER_SCHED };	/* Annealing schedule */

enum pic_type
{ NO_PICTURE, PLACEMENT, ROUTING };	/* What's on screen? */

/* For the placer.  Different types of cost functions that can be used. */

enum place_c_types
{ LINEAR_CONG, NONLINEAR_CONG };

enum e_operation
{ PLACE_AND_ROUTE, PLACE_ONLY, ROUTE_ONLY,
    TIMING_ANALYSIS_ONLY
};

enum pfreq
{ PLACE_NEVER, PLACE_ONCE, PLACE_ALWAYS };

/* Are the pads free to be moved, locked in a random configuration, or *
 * locked in user-specified positions?                                 */

enum e_pad_loc_type
{ FREE, RANDOM, USER };


struct s_net
{
    char *name;
    int num_sinks;
    int *node_block;
    int *node_block_pin;
    boolean is_global;
};


typedef struct s_T_subblock
{
    float **T_comb;
    float *T_seq_in;
    float *T_seq_out;
}
t_T_subblock;

/* Gives the delays through a subblock.                                    
 * T_comb: [0..num_inputs-1][0..num_outputs-1]
           The delay matrix from input to output when the subblock is used in     
 *         combinational mode (clock input is open).                       
 * T_seq_in: The setup time of the storage element without combinational delay
			 If the comb matrix changes for sequetial mode, 
			 account for that difference in the setup time 
 * T_seq_out: The delay from storage element to subblock output when the   
 *            subblock is in sequential mode.  Includes clock_to_Q plus    
 *            any combinational path (muxes, etc.) on the output.          */


typedef struct s_timing_inf
{
    boolean timing_analysis_enabled;
    float C_ipin_cblock;
    float T_ipin_cblock;
}
t_timing_inf;
typedef struct s_type_timing_inf
{
    float T_sblk_opin_to_sblk_ipin;
    float T_fb_ipin_to_sblk_ipin;
    float T_sblk_opin_to_fb_opin;
    t_T_subblock *T_subblock;
}
t_type_timing_inf;

/* C_ipin_cblock: Capacitance added to a routing track by the isolation     *
 *                buffer between a track and the Cblocks at an (i,j) loc.   *
 * T_ipin_cblock: Delay through an input pin connection box (from a         *
 *                   routing track to a logic block input pin).             *
 * T_sblk_opin_to_sblk_ipin: Delay through the local interconnect           *
 *       (muxes, wires or whatever) in a clb containing multiple subblocks. *
 *       That is, the delay from a subblock output to the input of another  *
 *       subblock in the same clb.                                          *
 * T_clb_ipin_to_sblk_ipin: Delay from a clb input pin to any subblock      *
 *                   input pin (e.g. the mux delay in an Altera 8K clb).    *
 * T_sblk_opin_to_clb_opin: Delay from a subblock output to a clb output.   *
 *                   Will be 0 in many architectures.                       *
 * T_ipad:  Delay through an input pad.                                     *
 * T_opad:  Delay through an output pad.                                    *
 * *T_subblock: Array giving the delay through each subblock.               *
 *              [0..max_subblocks_per_block - 1]                            */


enum e_grid_loc_type
{ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL };
struct s_grid_loc_def
{
    enum e_grid_loc_type grid_loc_type;
    int start_col;
    int repeat;
    float col_rel;
    int priority;
};

/* Defines how to place type in the grid 
	grid_loc_type - where the type goes and which numbers are valid
	start_col - the absolute value of the starting column from the left to fill, 
				used with COL_REPEAT
	repeat - the number of columns to skip before placing the same type, 
			used with COL_REPEAT.  0 means do not repeat
	rel_col - the fractional column to place type
	priority - in the event of conflict, which type gets picked?
*/


/* name:  ASCII net name for informative annotations in the output.          *
 * num_sinks:  Number of sinks on this net.                                  *
 * node_block: [0..num_sinks]. Contains the blocks to which the nodes of this 
 *         net connect.  The source block is node_block[0] and the sink blocks
 *         are the remaining nodes.
 * node_block_pin: [0..num_sinks]. Contains the number of the pin (on a block) to 
 *          which each net terminal connects. */

struct s_type_descriptor
{
    const char *name;
    int num_pins;
    int capacity;

    int height;
    int ***pinloc;		/* [0..height-1][0..3][0..num_pins-1] */

    int num_class;
    struct s_class *class_inf;	/* [0..num_class-1] */
    int *pin_class;		/* [0..num_pins-1] */

    boolean *is_global_pin;	/* [0..num_pins-1] */

    boolean is_Fc_frac;
    boolean is_Fc_out_full_flex;
    float Fc_in;
    float Fc_out;

    /* Subblock info */
    int max_subblocks;
    int max_subblock_inputs;
    int max_subblock_outputs;

    /* Grid location info */
    struct s_grid_loc_def *grid_loc_def;	/* [0..num_def-1] */
    int num_grid_loc_def;

    /* Timing info */
    t_type_timing_inf type_timing_inf;

    /* This info can be determined from class_inf and pin_class but stored for faster access */
    int num_drivers;
    int num_receivers;

    int index;			/* index of type descriptor in array (allows for index referencing) */
};
typedef struct s_type_descriptor t_type_descriptor;
typedef const struct s_type_descriptor *t_type_ptr;

/* Describes the type for a block
   name: unique identifier for type  
   num_pins: Number of pins for the block
   capacity: Number of blocks of this type that can occupy one grid tile.
             This is primarily used for IO pads.
   height: Height of large block in grid tiles
   pinloc: Is set to 1 if a given pin exists on a certain position of a block.
   num_class: Number of logically-equivalent pin classes
   class_inf: Information of each logically-equivalent class
   pin_class: The class a pin belongs to
   is_global_pin: Whether or not a pin is global (hence not routed)
   is_Fc_frac: True if Fc fractional, else Fc absolute
   is_Fc_out_full_flex: True means opins will connect to all available segments
*/

struct s_block
{
    char *name;
    t_type_ptr type;
    int *nets;
    int x;
    int y;
    int z;
};

/* name:  Taken from the net which it drives.                          *
 * type:  Pointer to type descriptor, NULL for illegal, IO_TYPE for io *
 * nets[]:  List of nets connected to this block.  If nets[i] = OPEN   *
            no net is connected to pin i.                              *
 * x,y:  Bottom physical location of the placed block.                 *
 * z:    Multiple independant locations within a physical location, 
         index to the blocks[] in s_grid_tile */


struct s_grid_tile
{
    t_type_ptr type;
    int offset;
    int usage;
    int *blocks;
};

/* s_grid_tile is the minimum tile of the fpga                         
 * type:  Pointer to type descriptor, NULL for illegal, IO_TYPE for io 
 * offset: Number of grid tiles above the bottom location of a block 
 * usage: Number of blocks used in this grid tile
 * blocks[]: Array of logical blocks placed in a physical position, EMPTY means
             no block at that index */


struct s_bb
{
    int xmin;
    int xmax;
    int ymin;
    int ymax;
};

/* Stores the bounding box of a net in terms of the minimum and  *
 * maximum coordinates of the blocks forming the net, clipped to *
 * the region (1..nx, 1..ny).                                    */


enum e_stat
{ UNIFORM, GAUSSIAN, PULSE, DELTA };
typedef struct s_chan
{
    enum e_stat type;
    float peak;
    float width;
    float xpeak;
    float dc;
}
t_chan;

/* Width is standard dev. for Gaussian.  xpeak is where peak     *
 * occurs. dc is the dc offset for Gaussian and pulse waveforms. */