ldpc_testbench.v

802.3an ldpc码编码、译码设计

/*
Copyright (c) 2007 Tom Hawkins

Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
*/
module ldpc_testbench;
  reg reset;  // Global, asynchronous active high reset.
  reg clock;  // Global clock.

  reg  [1722:0] input_data;        // Uncoded input data.
  wire [2047:0] coded_block;       // Encoded block.
  reg  [2047:0] bit_errors;        // Injected channel bit errors.
  wire [2047:0] nosy_block;        // Encoded block corrupted by channel noise.
  wire [2047:0] corrected_block;   // Corrected block.
  reg  load;                       // Load signal to LDPC decoder.
  wire decoded;                    // Convergence signal from LDPC decoder.
  wire [1722:0] output_data = corrected_block[1722:0];  // Decoded output data.

  integer iteration;   // Iteration counter.

  // LDPC Encoder
  ldpc_encoder_802_3an encoder
    ( .uncoded_block (input_data)
    , .coded_block   (coded_block)
    );

  // Nosy Channel
  assign nosy_block = coded_block ^ bit_errors;

  // LDPC Decoder
  ldpc_decoder_802_3an decoder
    ( .reset         (reset)
    , .clock         (clock)
    , .coded_block   (nosy_block)
    , .load          (load)
    , .decoded_block (corrected_block)
    , .decoded       (decoded)
    );

  // Reset and Clock Generation
  initial begin
    reset = 0;
    clock = 0;
    #1 reset = 1;
    #1 reset = 0;
    forever begin
      #1 clock = 1;
      #1 clock = 0;
    end
  end

  // Test Execution
  task ldpc_test;
    input [1722:0] data;   // Input data block.
    input [2047:0] errors; // Induced channel bit errors.
    begin
      $display ("New test...");
      $display ("  Input Data = 0x%0h", data);
      $display ("  Bit Errors = 0x%0h", errors);
      @ (negedge clock);
      load = 1;
      input_data = data;
      bit_errors = errors;
      @ (negedge clock);
      load = 0;
      iteration = 0;
      while (! decoded && iteration < 20) begin
        @ (negedge clock);
        iteration = iteration + 1;
      end
      if (decoded && input_data == output_data)
        $display("  Corrected block in %0d iterations.\n", iteration);
      else if (decoded)
        $display("  Parity check converged, but failed to corrected block in %0d iterations.\n", iteration);
      else
        $display("  Failed to converge after %0d iterations.\n", iteration);
    end
  endtask

  // Example Test Cases
  initial begin
    ldpc_test(1723'b0, 2048'b0);
    ldpc_test(1723'b0, 2048'b01);
    ldpc_test(1723'b0, 2048'b111111111);
    ldpc_test(1723'b0, 2048'b11110000000000000000000000000000000000000000000000000011110000000000000000000000000000000000000000001111);
    ldpc_test(1723'b0, 2048'b1111111111111111111111);
    ldpc_test(1723'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, 2048'b1111);
    $finish;
  end
endmodule