__projnav.log
来自「一个veriloghdl编写的键盘扫描程序」· LOG 代码 · 共 492 行
LOG
492 行
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "KeypadScan.v"Module <KeypadScan> compiledNo errors in compilationAnalysis of file <KeypadScan.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <KeypadScan>.Module <KeypadScan> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <KeypadScan>. Related source file is KeypadScan.v.WARNING:Xst:737 - Found 1-bit latch for signal <outreg_3>.WARNING:Xst:737 - Found 1-bit latch for signal <outreg_4>.WARNING:Xst:737 - Found 1-bit latch for signal <outreg_5>.WARNING:Xst:737 - Found 1-bit latch for signal <outreg_0>.WARNING:Xst:737 - Found 1-bit latch for signal <outreg_1>.WARNING:Xst:737 - Found 1-bit latch for signal <outreg_2>. Found 8-bit register for signal <shiftreg>.Unit <KeypadScan> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 1 8-bit register : 1# Latches : 6 1-bit latch : 6==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <KeypadScan> ... implementation constraint: INIT=s : shiftreg_7 implementation constraint: INIT=s : shiftreg_6 implementation constraint: INIT=r : shiftreg_0 implementation constraint: INIT=s : shiftreg_1 implementation constraint: INIT=s : shiftreg_2 implementation constraint: INIT=s : shiftreg_3 implementation constraint: INIT=s : shiftreg_4 implementation constraint: INIT=s : shiftreg_5Completed process "Synthesize".
Started process "Translate".Release 6.3.03i - ngdbuild G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc KeypadScan.ucf -p xbr KeypadScan.ngcKeypadScan.ngd Reading NGO file"c:/mikeg/designs/dan_cox/keypadscan_projnav_3_4_05/projnav/KeypadScan.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "KeypadScan.ucf" ...Attached a PULLUP primitive to pad net column<7> Attached a PULLUP primitive to pad net column<6> Attached a PULLUP primitive to pad net column<5> Attached a PULLUP primitive to pad net column<4> Attached a PULLUP primitive to pad net column<3> Attached a PULLUP primitive to pad net column<2> Attached a PULLUP primitive to pad net column<1> Attached a PULLUP primitive to pad net column<0> Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 37820 kilobytesWriting NGD file "KeypadScan.ngd" ...Writing NGDBUILD log file "KeypadScan.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.3.03i - CPLD Optimizer/Partitioner G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.WARNING:Cpld:960 - PULLUP specified for net 'column<7>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<6>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<5>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<4>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<3>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<2>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<1>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<0>' conflicts with previous KEEPER specification. PULLUP is ignored.Considering device XC2C32-6-CP56.WARNING:Cpld - The XC2C32 device is not recommended for new designs. The XC2C32A device is pin-compatible and is a functional superset of the XC2C32, and should be used as a replacement.Re-checking device resources ......Synthesizing and Optimizing..................................................................................................o.......Fitting...........oDesign KeypadScan has been optimized and fit into device XC2C32-6-CP56.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Fit".Release 6.3.03i - CPLD Optimizer/Partitioner G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.WARNING:Cpld:960 - PULLUP specified for net 'column<7>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<6>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<5>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<4>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<3>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<2>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<1>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<0>' conflicts with previous KEEPER specification. PULLUP is ignored.Considering device XC2C32A-6-CP56.Re-checking device resources ......Synthesizing and Optimizing..................................................................................................o.......Fitting...........oDesign KeypadScan has been optimized and fit into device XC2C32A-6-CP56.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Release 6.3.03i - ngdbuild G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc KeypadScan.ucf -p xbr KeypadScan.ngcKeypadScan.ngd Reading NGO file"c:/mikeg/designs/dan_cox/keypadscan_projnav_3_4_05/projnav/KeypadScan.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "KeypadScan.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 37820 kilobytesWriting NGD file "KeypadScan.ngd" ...Writing NGDBUILD log file "KeypadScan.bld"...NGDBUILD done.Completed process "Translate".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Release 6.3.03i - ngdbuild G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc KeypadScan.ucf -p xbr KeypadScan.ngcKeypadScan.ngd Reading NGO file"c:/mikeg/designs/dan_cox/keypadscan_projnav_3_4_05/projnav/KeypadScan.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "KeypadScan.ucf" ...Attached a PULLUP primitive to pad net column<7> Attached a PULLUP primitive to pad net column<6> Attached a PULLUP primitive to pad net column<5> Attached a PULLUP primitive to pad net column<4> Attached a PULLUP primitive to pad net column<3> Attached a PULLUP primitive to pad net column<2> Attached a PULLUP primitive to pad net column<1> Attached a PULLUP primitive to pad net column<0> Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 37820 kilobytesWriting NGD file "KeypadScan.ngd" ...Writing NGDBUILD log file "KeypadScan.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.3.03i - CPLD Optimizer/Partitioner G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.WARNING:Cpld:960 - PULLUP specified for net 'column<7>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<6>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<5>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<4>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<3>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<2>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<1>' conflicts with previous KEEPER specification. PULLUP is ignored.WARNING:Cpld:960 - PULLUP specified for net 'column<0>' conflicts with previous KEEPER specification. PULLUP is ignored.Considering device XC2C32A-6-CP56.Re-checking device resources ......Synthesizing and Optimizing..................................................................................................o.......Fitting...........oDesign KeypadScan has been optimized and fit into device XC2C32A-6-CP56.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Fit".Release 6.3.03i - CPLD Optimizer/Partitioner G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Considering device XC2C32A-6-CP56.Re-checking device resources ......Synthesizing and Optimizing..................................................................................................o.......Fitting...........oDesign KeypadScan has been optimized and fit into device XC2C32A-6-CP56.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Release 6.3.03i - ngdbuild G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc KeypadScan.ucf -p xbr KeypadScan.ngcKeypadScan.ngd Reading NGO file"c:/mikeg/designs/dan_cox/keypadscan_projnav_3_4_05/projnav/KeypadScan.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "KeypadScan.ucf" ...Attached a PULLUP primitive to pad net column<7> Attached a PULLUP primitive to pad net column<6> Attached a PULLUP primitive to pad net column<5> Attached a PULLUP primitive to pad net column<4> Attached a PULLUP primitive to pad net column<3> Attached a PULLUP primitive to pad net column<2> Attached a PULLUP primitive to pad net column<1> Attached a PULLUP primitive to pad net column<0> Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 37820 kilobytesWriting NGD file "KeypadScan.ngd" ...Writing NGDBUILD log file "KeypadScan.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.3.03i - CPLD Optimizer/Partitioner G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Considering device XC2C32A-6-CP56.Re-checking device resources ......Synthesizing and Optimizing..................................................................................................o.......Fitting...........oDesign KeypadScan has been optimized and fit into device XC2C32A-6-CP56.Completed process "Fit".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Post-Fit Simulation Model".Release 6.3.03i - CPLD Timing Simulation Interface G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Creating NGA for simulation.Speed File: Version 9.0 Advance Product SpecificationCompleted process "Generate Post-Fit Simulation Model".
Release 6.3.03i - netgen G.38Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Reading design KeypadScan.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ...Writing Verilog SDF file KeypadScan_timesim.sdf ...Writing Verilog netlist file KeypadScan_timesim.v ...INFO:NetListWriters:580 - If Verilog simulation is performed outside the ISE Project Navigator environment, please add $XILINX/verilog/src/glbl.v to the simulator compile and invocation commands in order to allow proper initialization of the design. If simulation is performed within Project Navigator, this will be taken care of automatically. For more information on compiling and performing Xilinx simulation, consult the online Synthesis and Simulation Design Guide: http://support.xilinx.com/support/software_manuals.htm Total memory usage is 34504 kilobytesCreated netgen log file 'KeypadScan_timesim.nlf'.Completed process "Generate Post-Fit Simulation Model".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
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