ex9.out

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Reading in the Synopsys vhdl primitives.
Warning: Variable 'full' is being read 
	in routine EX9 line 18 in file 'D:/temp/eda6000/xc95/ex9/ex9.vhd', 
	but is not in the process sensitivity list of the block which begins 
	there.   (HDL-179)

Inferred memory devices in process 'p_reg'
	in routine EX9 line 18 in file
         'D:/temp/eda6000/xc95/ex9/ex9.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      cnt8_reg       | Flip-flop |   8   |  Y  | N  | N  | N  | N  | N  | N  |
|      full_reg       | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
===============================================================================

cnt8_reg (width 8)
------------------
    set/reset/toggle: none


full_reg
--------
    set/reset/toggle: none



Inferred memory devices in process 'p_div'
	in routine EX9 line 34 in file
         'D:/temp/eda6000/xc95/ex9/ex9.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       cnt_reg       | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | Y  |
|      fout_reg       | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | N  |
===============================================================================

cnt_reg
-------
    Sync-toggle: true


fout_reg
--------
    set/reset/toggle: none


Writing to hnl file 'd:\temp\EDA6000\XC95\EX9\ex9/workdirs/WORK/EX9.hnl'