time_sim.edn
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· EDN 代码 · 共 1,611 行 · 第 1/5 页
EDN
1,611 行
(edif ex9 (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timestamp 2008 3 12 12 3 42) (program "Xilinx ngd2edif" (version "E.38")) (comment "Command line: -w -v fndtn ex9.nga time_sim.edn "))) (external SIMPRIMS (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit TIME)))) (cell x_opad (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port PAD (direction OUTPUT) ) ) ) ) (cell x_buf (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_ff (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN (direction INPUT) ) (port CE (direction INPUT) ) (port CLK (direction INPUT) ) (port SET (direction INPUT) ) (port RST (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_one (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port OUT (direction OUTPUT) ) ) ) ) (cell x_zero (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port OUT (direction OUTPUT) ) ) ) ) (cell x_or2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_and8 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port IN2 (direction INPUT) ) (port IN3 (direction INPUT) ) (port IN4 (direction INPUT) ) (port IN5 (direction INPUT) ) (port IN6 (direction INPUT) ) (port IN7 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_xor2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_and16 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port IN2 (direction INPUT) ) (port IN3 (direction INPUT) ) (port IN4 (direction INPUT) ) (port IN5 (direction INPUT) ) (port IN6 (direction INPUT) ) (port IN7 (direction INPUT) ) (port IN8 (direction INPUT) ) (port IN9 (direction INPUT) ) (port IN10 (direction INPUT) ) (port IN11 (direction INPUT) ) (port IN12 (direction INPUT) ) (port IN13 (direction INPUT) ) (port IN14 (direction INPUT) ) (port IN15 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_and2 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_and7 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port IN2 (direction INPUT) ) (port IN3 (direction INPUT) ) (port IN4 (direction INPUT) ) (port IN5 (direction INPUT) ) (port IN6 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_or3 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port IN2 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_and6 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) ) (port IN2 (direction INPUT) ) (port IN3 (direction INPUT) ) (port IN4 (direction INPUT) ) (port IN5 (direction INPUT) ) (port OUT (direction OUTPUT) ) ) ) ) (cell x_or4 (cellType GENERIC) (view view_1 (viewType NETLIST) (interface (port IN0 (direction INPUT) ) (port IN1 (direction INPUT) )
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