ex9.gyd

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Pin Freeze File:  version E.38

957284 XC9572-7-PC84
clk S:PIN10
d<0> S:PIN20
d<1> S:PIN23
d<2> S:PIN24
d<3> S:PIN25
d<4> S:PIN26
d<5> S:PIN31
d<6> S:PIN34
d<7> S:PIN32
fout S:PIN56
pfull S:PIN52


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.




PARTITION FB4_4 N_pfull
PARTITION FB4_9 "cnt8<0>" "cnt8<7>" "cnt8<1>" cnt
		 "cnt8<6>" N_fout "cnt8<2>" "cnt8<5>"
		 "cnt8<3>" "cnt8<4>"