ex9.data

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "ex9";

/* port drive, load, max capacitance and max transition in data file */
PORTDATA
clk: MAXTRANS(0.0);
d<1>: MAXTRANS(0.0);
d<0>: MAXTRANS(0.0);
d<2>: MAXTRANS(0.0);
d<3>: MAXTRANS(0.0);
d<6>: MAXTRANS(0.0);
d<4>: MAXTRANS(0.0);
d<5>: MAXTRANS(0.0);
d<7>: MAXTRANS(0.0);
pfull: MAXTRANS(0.0);
fout: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
clk_pfull_delay:
CELL_RISE(scalar) {
  VALUES("4.5");
}
CELL_FALL(scalar) {
  VALUES("4.5");
}
ENDARCDATA

ARCDATA
clk_fout_delay:
CELL_RISE(scalar) {
  VALUES("12");
}
CELL_FALL(scalar) {
  VALUES("12");
}
ENDARCDATA

ARCDATA
d<0>_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
d<1>_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
d<2>_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
d<3>_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
d<4>_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
d<5>_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
d<6>_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
d<7>_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
d<0>_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ARCDATA
d<1>_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ARCDATA
d<2>_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ARCDATA
d<3>_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ARCDATA
d<4>_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ARCDATA
d<5>_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ARCDATA
d<6>_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ARCDATA
d<7>_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-1.5");
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA