📄 ex9.rpt
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cnt8<2> 3 0 0 2 FB4_15 STD 65 I/O (b)
cnt8<5> 4 0 0 1 FB4_16 STD 62 I/O (b)
cnt8<3> 4 0 0 1 FB4_17 STD 66 I/O (b)
cnt8<4> 5 0 0 0 FB4_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "d<0>" 7: "d<6>" 13: "cnt8<2>.FBK".LFBK
2: "d<1>" 8: "d<7>" 14: "cnt8<3>.FBK".LFBK
3: "d<2>" 9: N_pfull.FBK.LFBK 15: "cnt8<4>.FBK".LFBK
4: "d<3>" 10: cnt.FBK.LFBK 16: "cnt8<5>.FBK".LFBK
5: "d<4>" 11: "cnt8<0>.FBK".LFBK
17: "cnt8<6>.FBK".LFBK
6: "d<5>" 12: "cnt8<1>.FBK".LFBK
18: "cnt8<7>.FBK".LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
pfull ..........XXXXXXXX...................... 8 8
cnt8<0> X.........XXXXXXXX...................... 9 9
cnt8<7> .......X..XXXXXXXX...................... 9 9
cnt8<1> .X........XXXXXXXX...................... 9 9
cnt ........XX.............................. 2 2
cnt8<6> ......X...XXXXXXXX...................... 9 9
fout ........XX.............................. 2 2
cnt8<2> ..X.......XXXXXXXX...................... 9 9
cnt8<5> .....X....XXXXXXXX...................... 9 9
cnt8<3> ...X......XXXXXXXX...................... 9 9
cnt8<4> ....X.....XXXXXXXX...................... 9 9
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
fout := /cnt.FBK.LFBK
fout.CLKF = N_pfull.FBK.LFBK
fout.PRLD = GND
pfull := "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<6>.FBK".LFBK *
"cnt8<4>.FBK".LFBK * "cnt8<5>.FBK".LFBK * "cnt8<7>.FBK".LFBK
pfull.CLKF = clk ;FCLK/GCK
pfull.PRLD = GND
cnt := /cnt.FBK.LFBK
cnt.CLKF = N_pfull.FBK.LFBK
cnt.PRLD = GND
/"cnt8<0>".T = "d<0>" * "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<6>.FBK".LFBK *
"cnt8<4>.FBK".LFBK * "cnt8<5>.FBK".LFBK * "cnt8<7>.FBK".LFBK
"cnt8<0>".CLKF = clk ;FCLK/GCK
"cnt8<0>".PRLD = GND
/"cnt8<1>".T = /"cnt8<0>.FBK".LFBK
+ "d<1>" * "cnt8<1>.FBK".LFBK * "cnt8<2>.FBK".LFBK *
"cnt8<3>.FBK".LFBK * "cnt8<6>.FBK".LFBK * "cnt8<4>.FBK".LFBK *
"cnt8<5>.FBK".LFBK * "cnt8<7>.FBK".LFBK
"cnt8<1>".CLKF = clk ;FCLK/GCK
"cnt8<1>".PRLD = GND
/"cnt8<2>".T = /"cnt8<1>.FBK".LFBK
+ /"cnt8<0>.FBK".LFBK
+ "d<2>" * "cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK *
"cnt8<6>.FBK".LFBK * "cnt8<4>.FBK".LFBK * "cnt8<5>.FBK".LFBK *
"cnt8<7>.FBK".LFBK
"cnt8<2>".CLKF = clk ;FCLK/GCK
"cnt8<2>".PRLD = GND
/"cnt8<3>".T = /"cnt8<1>.FBK".LFBK
+ /"cnt8<0>.FBK".LFBK
+ /"cnt8<2>.FBK".LFBK
+ "d<3>" * "cnt8<3>.FBK".LFBK * "cnt8<6>.FBK".LFBK *
"cnt8<4>.FBK".LFBK * "cnt8<5>.FBK".LFBK * "cnt8<7>.FBK".LFBK
"cnt8<3>".CLKF = clk ;FCLK/GCK
"cnt8<3>".PRLD = GND
"cnt8<4>".T = /"d<4>" * "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * /"cnt8<6>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * /"cnt8<4>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * /"cnt8<5>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * /"cnt8<7>.FBK".LFBK
"cnt8<4>".CLKF = clk ;FCLK/GCK
"cnt8<4>".PRLD = GND
"cnt8<5>".T = /"d<5>" * "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<4>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * /"cnt8<6>.FBK".LFBK *
"cnt8<4>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<4>.FBK".LFBK *
/"cnt8<5>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<4>.FBK".LFBK *
/"cnt8<7>.FBK".LFBK
"cnt8<5>".CLKF = clk ;FCLK/GCK
"cnt8<5>".PRLD = GND
"cnt8<6>".T = /"d<6>" * "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<4>.FBK".LFBK *
"cnt8<5>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * /"cnt8<6>.FBK".LFBK *
"cnt8<4>.FBK".LFBK * "cnt8<5>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<4>.FBK".LFBK *
"cnt8<5>.FBK".LFBK * /"cnt8<7>.FBK".LFBK
"cnt8<6>".CLKF = clk ;FCLK/GCK
"cnt8<6>".PRLD = GND
"cnt8<7>".T = /"d<7>" * "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<6>.FBK".LFBK *
"cnt8<4>.FBK".LFBK * "cnt8<5>.FBK".LFBK
+ "cnt8<1>.FBK".LFBK * "cnt8<0>.FBK".LFBK *
"cnt8<2>.FBK".LFBK * "cnt8<3>.FBK".LFBK * "cnt8<6>.FBK".LFBK *
"cnt8<4>.FBK".LFBK * "cnt8<5>.FBK".LFBK * /"cnt8<7>.FBK".LFBK
"cnt8<7>".CLKF = clk ;FCLK/GCK
"cnt8<7>".PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9572-7-PC84
T c T G T T T T T T T T T T T T T V T T T
I l I N I I I I I I I I I I I I I C I I I
E k E D E E E E E E E E E E E E E C E E E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | TIE
TIE | 15 71 | TIE
GND | 16 70 | TIE
TIE | 17 69 | TIE
TIE | 18 68 | TIE
TIE | 19 67 | TIE
d<0> | 20 66 | TIE
TIE | 21 XC9572-7-PC84 65 | TIE
VCC | 22 64 | VCC
d<1> | 23 63 | TIE
d<2> | 24 62 | TIE
d<3> | 25 61 | TIE
d<4> | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | TIE
TMS | 29 57 | TIE
TCK | 30 56 | fout
d<5> | 31 55 | TIE
d<7> | 32 54 | TIE
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
T d T T T V T T T G T T T T T T G T T p T
I < I I I C I I I N I I I I I I N I I f I
E 6 E E E C E E E D E E E E E E D E E u E
> l
l
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9572-7-PC84
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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