ex9.mod

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex9";

/* port names and type */
INPUT S:PIN10 = clk;
INPUT S:PIN23 = d<1>;
INPUT S:PIN20 = d<0>;
INPUT S:PIN24 = d<2>;
INPUT S:PIN25 = d<3>;
INPUT S:PIN34 = d<6>;
INPUT S:PIN26 = d<4>;
INPUT S:PIN31 = d<5>;
INPUT S:PIN32 = d<7>;
OUTPUT S:PIN52 = pfull;
OUTPUT S:PIN56 = fout;

/* timing arc definitions */
clk_pfull_delay: DELAY clk pfull;
clk_fout_delay: DELAY clk fout;

/* timing check arc definitions */
d<0>_clk_setup: SETUP(POSEDGE) d<0> clk;
d<1>_clk_setup: SETUP(POSEDGE) d<1> clk;
d<2>_clk_setup: SETUP(POSEDGE) d<2> clk;
d<3>_clk_setup: SETUP(POSEDGE) d<3> clk;
d<4>_clk_setup: SETUP(POSEDGE) d<4> clk;
d<5>_clk_setup: SETUP(POSEDGE) d<5> clk;
d<6>_clk_setup: SETUP(POSEDGE) d<6> clk;
d<7>_clk_setup: SETUP(POSEDGE) d<7> clk;
d<0>_clk_hold: HOLD(POSEDGE) d<0> clk;
d<1>_clk_hold: HOLD(POSEDGE) d<1> clk;
d<2>_clk_hold: HOLD(POSEDGE) d<2> clk;
d<3>_clk_hold: HOLD(POSEDGE) d<3> clk;
d<4>_clk_hold: HOLD(POSEDGE) d<4> clk;
d<5>_clk_hold: HOLD(POSEDGE) d<5> clk;
d<6>_clk_hold: HOLD(POSEDGE) d<6> clk;
d<7>_clk_hold: HOLD(POSEDGE) d<7> clk;

ENDMODEL