ex9.tim

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                           Performance Summary Report
                           --------------------------

Design:     ex9
Device:     XC9572-7-PC84
Speed File: Version 3.0
Program:    Timing Report Generator:  version E.38
Date:       Thu Mar 13 13:58:09 2008

Performance Summary: 

Clock net 'pfull.Q' path delays:

Clock to Setup (tCYC)                     :          8.0ns (1 macrocell levels)
Clock to Q, net 'cnt.Q' to DFF Setup(D) at 'cnt.D'                (Pterm Clock)

                          Minimum Clock Period: 10.0ns
                     Maximum Internal Clock Speed: 100.0Mhz
                         (Limited by Clock Pulse Width)

Clock net 'clk' path delays:

Clock Pad to Output Pad (tCO)             :         12.0ns (1 macrocell levels)
Clock Pad 'clk' to Output Pad 'fout'                                      (GCK)

Clock to Setup (tCYC)                     :          8.0ns (1 macrocell levels)
Clock to Q, net 'cnt8<1>.Q' to DFF Setup(D) at 'pfull.D'                  (GCK)
Target FF drives output net 'N_pfull$Q'

Setup to Clock at the Pad (tSU)           :          4.5ns (0 macrocell levels)
Data signal 'd<1>' to TFF D input Pin at 'cnt8<1>.D'
Clock pad 'clk'                                                           (GCK)

                          Minimum Clock Period: 8.0ns
                     Maximum Internal Clock Speed: 125.0Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                      Clock Pad to Output Pad (tCO) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

fout     12.0
pfull     4.5

--------------------------------------------------------------------------------
                       Setup to Clock at Pad (tSU) (nsec)

\ From      c
 \          l
  \         k
   \         
    \        
     \       
      \      
  To   \------

d<0>      4.5
d<1>      4.5
d<2>      4.5
d<3>      4.5
d<4>      4.5
d<5>      4.5
d<6>      4.5
d<7>      4.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                               (Clock: N_pfull.Q)

\ From      c
 \          n
  \         t
   \        .
    \       Q
     \       
      \      
  To   \------

cnt.D     8.0
fout.D    8.0

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                                  (Clock: clk)

\ From        c     c     c     c     c     c     c     c
 \            n     n     n     n     n     n     n     n
  \           t     t     t     t     t     t     t     t
   \          8     8     8     8     8     8     8     8
    \         <     <     <     <     <     <     <     <
     \        0     1     2     3     4     5     6     7
      \       >     >     >     >     >     >     >     >
       \      .     .     .     .     .     .     .     .
        \     Q     Q     Q     Q     Q     Q     Q     Q
  To     \------------------------------------------------

cnt8<0>.D   8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0
cnt8<1>.D   8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0
cnt8<2>.D   8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0
cnt8<3>.D   8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0
cnt8<4>.D   8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0
cnt8<5>.D   8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0
cnt8<6>.D   8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0
cnt8<7>.D   8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0
pfull.D     8.0   8.0   8.0   8.0   8.0   8.0   8.0   8.0

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU) -             Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and end at register D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.