time_sim.edn

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

(edif ex9
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timestamp 2008 3 13 13 58 12)
      (program "Xilinx ngd2edif" (version "E.38"))
      (comment "Command line: -w -v fndtn ex9.nga time_sim.edn ")))
  (external SIMPRIMS
    (edifLevel 0)
    (technology (numberDefinition
      (scale 1 (E 1 -12) (unit TIME))))
    (cell x_opad
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port PAD
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_buf
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_ff
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN
              (direction INPUT)
            )
            (port CE
              (direction INPUT)
            )
            (port CLK
              (direction INPUT)
            )
            (port SET
              (direction INPUT)
            )
            (port RST
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_one
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_zero
      (cellType GENERIC)
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          (viewType NETLIST)
          (interface
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
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      (cellType GENERIC)
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              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
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              (direction OUTPUT)
            )
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    )
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              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
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              (direction INPUT)
            )
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              (direction INPUT)
            )
            (port IN5
              (direction INPUT)
            )
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              (direction INPUT)
            )
            (port IN7
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
    (cell x_xor2
      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
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      )
    )
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      (cellType GENERIC)
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              (direction INPUT)
            )
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              (direction INPUT)
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              (direction INPUT)
            )
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              (direction INPUT)
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              (direction INPUT)
            )
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              (direction INPUT)
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              (direction INPUT)
            )
            (port IN8
              (direction INPUT)
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              (direction INPUT)
            )
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              (direction INPUT)
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            (port IN11
              (direction INPUT)
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              (direction INPUT)
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              (direction INPUT)
            )
            (port IN14
              (direction INPUT)
            )
            (port IN15
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
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            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
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          )
      )
    )
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      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
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      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
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              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
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      (cellType GENERIC)
        (view view_1
          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port IN4
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )
      )
    )
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      (cellType GENERIC)
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          (viewType NETLIST)
          (interface
            (port IN0
              (direction INPUT)
            )
            (port IN1
              (direction INPUT)
            )
            (port IN2
              (direction INPUT)
            )
            (port IN3
              (direction INPUT)
            )
            (port IN4
              (direction INPUT)
            )
            (port IN5
              (direction INPUT)
            )
            (port OUT
              (direction OUTPUT)
            )
          )