testctl.out

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

Inferred memory devices in process 
	in routine testctl line 16 in file
         'D:/temp/EDA6000/XC95/ex10sch/testctl.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|     div2clk_reg     | Flip-flop |   1   |  -  | -  | N  | N  | N  | N  | Y  |
===============================================================================

div2clk_reg
-----------
    Sync-toggle: true


Writing to hnl file 'D:\temp\EDA6000\XC95\ex10sch\DPMCOMP.TMP/workdirs/WORK/testctl.hnl'