ex10sch.gyd

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· GYD 代码 · 共 42 行

Pin Freeze File:  version E.38

957284 XC9572-10-PC84
CLK S:PIN32
UCLK S:PIN31
\$Net00009_ S:PIN40
\$Net00046_ S:PIN41
\$Net00047_ S:PIN33
\$Net00042_ S:PIN43
\$Net00044_ S:PIN44
\$Net00041_ S:PIN45
\$Net00043_ S:PIN46
\$Net00045_ S:PIN47
\$Net00050_ S:PIN57
\$Net00048_ S:PIN58
\$Net00049_ S:PIN50
\$Net00051_ S:PIN51
\$Net00039_ S:PIN52
\$Net00037_ S:PIN53
\$Net00038_ S:PIN54
\$Net00040_ S:PIN55


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_15 "\$Net00002_" "&__A__8" "&__A__4" "&__A__2"
		

PARTITION FB3_3 "&__A__6" "&__A__16" "&__A__14" "&__A__12"
		 "&__A__10" "\$Net00006_" "\$Net00005_" "LA<0>"
		 "LA<2>" "LA<1>" "LA<3>" "&__A__9"
		 "&__A__13" "LB<1>" "&__A__15" "&__A__11"
		
PARTITION FB4_1 "LB<2>" "LB<0>" "LC<3>" "LD<0>"
		 "LB<3>" "LD<2>" "LD<3>"
PARTITION FB4_9 "LC<2>" "LC<0>" "LD<1>" "LC<1>"
		
PARTITION FB4_14 "\$Net00004_" "&__A__5" "&__A__1" "&__A__7"
		 "&__A__3"