ex10sch.data

[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][

MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "ex10sch";

/* port drive, load, max capacitance and max transition in data file */
PORTDATA
CLK: MAXTRANS(0.0);
UCLK: MAXTRANS(0.0);
\$Net00009_: MAXTRANS(0.0);
\$Net00046_: MAXTRANS(0.0);
\$Net00047_: MAXTRANS(0.0);
\$Net00042_: MAXTRANS(0.0);
\$Net00044_: MAXTRANS(0.0);
\$Net00041_: MAXTRANS(0.0);
\$Net00043_: MAXTRANS(0.0);
\$Net00045_: MAXTRANS(0.0);
\$Net00050_: MAXTRANS(0.0);
\$Net00048_: MAXTRANS(0.0);
\$Net00049_: MAXTRANS(0.0);
\$Net00051_: MAXTRANS(0.0);
\$Net00039_: MAXTRANS(0.0);
\$Net00037_: MAXTRANS(0.0);
\$Net00038_: MAXTRANS(0.0);
\$Net00040_: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
CLK_\$Net00009__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00046__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00047__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00042__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00044__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00041__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00043__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00045__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00050__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00048__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00049__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00051__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00039__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00037__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00038__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ARCDATA
CLK_\$Net00040__delay:
CELL_RISE(scalar) {
  VALUES("23");
}
CELL_FALL(scalar) {
  VALUES("23");
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA