ex10sch.mod

来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· MOD 代码 · 共 46 行

MODEL
MODEL_VERSION "v1998.8";
DESIGN "ex10sch";

/* port names and type */
INPUT S:PIN32 = CLK;
INPUT S:PIN31 = UCLK;
OUTPUT S:PIN40 = \$Net00009_;
OUTPUT S:PIN41 = \$Net00046_;
OUTPUT S:PIN33 = \$Net00047_;
OUTPUT S:PIN43 = \$Net00042_;
OUTPUT S:PIN44 = \$Net00044_;
OUTPUT S:PIN45 = \$Net00041_;
OUTPUT S:PIN46 = \$Net00043_;
OUTPUT S:PIN47 = \$Net00045_;
OUTPUT S:PIN57 = \$Net00050_;
OUTPUT S:PIN58 = \$Net00048_;
OUTPUT S:PIN50 = \$Net00049_;
OUTPUT S:PIN51 = \$Net00051_;
OUTPUT S:PIN52 = \$Net00039_;
OUTPUT S:PIN53 = \$Net00037_;
OUTPUT S:PIN54 = \$Net00038_;
OUTPUT S:PIN55 = \$Net00040_;

/* timing arc definitions */
CLK_\$Net00009__delay: DELAY CLK \$Net00009_;
CLK_\$Net00046__delay: DELAY CLK \$Net00046_;
CLK_\$Net00047__delay: DELAY CLK \$Net00047_;
CLK_\$Net00042__delay: DELAY CLK \$Net00042_;
CLK_\$Net00044__delay: DELAY CLK \$Net00044_;
CLK_\$Net00041__delay: DELAY CLK \$Net00041_;
CLK_\$Net00043__delay: DELAY CLK \$Net00043_;
CLK_\$Net00045__delay: DELAY CLK \$Net00045_;
CLK_\$Net00050__delay: DELAY CLK \$Net00050_;
CLK_\$Net00048__delay: DELAY CLK \$Net00048_;
CLK_\$Net00049__delay: DELAY CLK \$Net00049_;
CLK_\$Net00051__delay: DELAY CLK \$Net00051_;
CLK_\$Net00039__delay: DELAY CLK \$Net00039_;
CLK_\$Net00037__delay: DELAY CLK \$Net00037_;
CLK_\$Net00038__delay: DELAY CLK \$Net00038_;
CLK_\$Net00040__delay: DELAY CLK \$Net00040_;

/* timing check arc definitions */

ENDMODEL