📄 ex10sch.tim
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Performance Summary Report
--------------------------
Design: ex10sch
Device: XC9572-10-PC84
Speed File: Version 3.0
Program: Timing Report Generator: version E.38
Date: Sat Mar 15 01:18:14 2008
Performance Summary:
Clock net '\$Net00002_.Q' path delays:
Minimum Clock Period: 12.0ns
Maximum Internal Clock Speed: 83.3Mhz
(Limited by Clock Pulse Width)
Clock net 'CLK' path delays:
Clock Pad to Output Pad (tCO) : 23.0ns (1 macrocell levels)
Clock Pad 'CLK' to Output Pad '\$Net00009_' (Pterm Clock)
Clock to Setup (tCYC) : 9.0ns (1 macrocell levels)
Clock to Q, net '\$Net00002_.Q' to DFF Setup(D) at '\$Net00002_.D'(Pterm Clock)
Target FF drives output net '\$Net00002_'
Minimum Clock Period: 12.0ns
Maximum Internal Clock Speed: 83.3Mhz
(Limited by Clock Pulse Width)
Clock net '\$Net00005_.Q' path delays:
Clock to Setup (tCYC) : 15.0ns (1 macrocell levels)
Clock to Q, net '&__A__8.Q' to TFF Setup(D) at '&__A__7.D' (Pterm Clock)
Target FF drives output net '&__A__7'
Minimum Clock Period: 15.0ns
Maximum Internal Clock Speed: 66.6Mhz
(Limited by Cycle Time)
Clock net '\$Net00004_.Q' path delays:
Clock to Setup (tCYC) : 15.0ns (1 macrocell levels)
Clock to Q, net '&__A__4.Q' to TFF Setup(D) at '&__A__3.D' (Pterm Clock)
Target FF drives output net '&__A__3'
Minimum Clock Period: 15.0ns
Maximum Internal Clock Speed: 66.6Mhz
(Limited by Cycle Time)
Clock net 'UCLK' path delays:
Clock to Setup (tCYC) : 9.0ns (1 macrocell levels)
Clock to Q, net '&__A__15.Q' to TFF Setup(D) at '&__A__15.D' (Pterm Clock)
Minimum Clock Period: 12.0ns
Maximum Internal Clock Speed: 83.3Mhz
(Limited by Clock Pulse Width)
Clock net '\$Net00006_.Q' path delays:
Clock to Setup (tCYC) : 9.0ns (1 macrocell levels)
Clock to Q, net '&__A__11.Q' to TFF Setup(D) at '&__A__11.D' (Pterm Clock)
Minimum Clock Period: 12.0ns
Maximum Internal Clock Speed: 83.3Mhz
(Limited by Clock Pulse Width)
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From C
\ L
\ K
\
\
\
\
\
\
\
\
To \------
\$Net00009_ 23.0
\$Net00037_ 23.0
\$Net00038_ 23.0
\$Net00039_ 23.0
\$Net00040_ 23.0
\$Net00041_ 23.0
\$Net00042_ 23.0
\$Net00043_ 23.0
\$Net00044_ 23.0
\$Net00045_ 23.0
\$Net00046_ 23.0
\$Net00047_ 23.0
\$Net00048_ 23.0
\$Net00049_ 23.0
\$Net00050_ 23.0
\$Net00051_ 23.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: CLK)
\ From \
\ $
\ N
\ e
\ t
\ 0
\ 0
\ 0
\ 0
\ 2
\ _
\ .
\ Q
To \------
\$Net00002_.D 9.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: \$Net00005_.Q)
\ From & & & & \
\ _ _ _ _ $
\ _ _ _ _ N
\ A A A A e
\ _ _ _ _ t
\ _ _ _ _ 0
\ 5 6 7 8 0
\ . . . . 0
\ Q Q Q Q 0
\ 4
\ _
\ .
\ Q
To \------------------------------
&__A__5.D 9.0 15.0 9.0 15.0
&__A__6.D 15.0 15.0
&__A__7.D 9.0 15.0 9.0 15.0
\$Net00004_.D 9.0 15.0 9.0 15.0 9.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: \$Net00004_.Q)
\ From & & & &
\ _ _ _ _
\ _ _ _ _
\ A A A A
\ _ _ _ _
\ _ _ _ _
\ 1 2 3 4
\ . . . .
\ Q Q Q Q
To \------------------------
&__A__1.D 9.0 15.0 9.0 15.0
&__A__2.D 15.0 9.0
&__A__3.D 9.0 15.0 9.0 15.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: UCLK)
\ From & & & & \
\ _ _ _ _ $
\ _ _ _ _ N
\ A A A A e
\ _ _ _ _ t
\ _ _ _ _ 0
\ 1 1 1 1 0
\ 3 4 5 6 0
\ . . . . 0
\ Q Q Q Q 6
\ _
\ .
\ Q
To \------------------------------
&__A__13.D 9.0 9.0 9.0 9.0
&__A__14.D 9.0 9.0
&__A__15.D 9.0 9.0 9.0 9.0
\$Net00006_.D 9.0 9.0 9.0 9.0 9.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: \$Net00006_.Q)
\ From & & & & \
\ _ _ _ _ $
\ _ _ _ _ N
\ A A A A e
\ _ _ _ _ t
\ _ _ _ _ 0
\ 1 1 1 9 0
\ 0 1 2 . 0
\ . . . Q 0
\ Q Q Q 5
\ _
\ .
\ Q
To \------------------------------
&__A__10.D 9.0 9.0
&__A__11.D 9.0 9.0 9.0 9.0
&__A__9.D 9.0 9.0 9.0 9.0
\$Net00005_.D 9.0 9.0 9.0 9.0 9.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and end at register D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU.
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