ex10sch.rpt
来自「[VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加」· RPT 代码 · 共 620 行 · 第 1/3 页
RPT
620 行
"&__A__7.FBK".LFBK
+ "&__A__8" * /"&__A__6" * "\$Net00002_" *
/"&__A__7.FBK".LFBK * "&__A__5.FBK".LFBK
"&__A__5".CLKF = "\$Net00005_"
"&__A__5".RSTF = /CLK * /"\$Net00002_"
"&__A__5".PRLD = GND
"&__A__6".T = "&__A__7" * "&__A__8" * "\$Net00002_"
"&__A__6".CLKF = "\$Net00005_.FBK".LFBK
"&__A__6".RSTF = /CLK * /"\$Net00002_"
"&__A__6".PRLD = GND
/"&__A__7".T = /"&__A__8"
+ /"\$Net00002_"
+ /"&__A__6" * /"&__A__7.FBK".LFBK *
"&__A__5.FBK".LFBK
"&__A__7".CLKF = "\$Net00005_"
"&__A__7".RSTF = /CLK * /"\$Net00002_"
"&__A__7".PRLD = GND
"&__A__8".T = "\$Net00002_.FBK".LFBK
"&__A__8".CLKF = "\$Net00005_"
"&__A__8".RSTF = /CLK * /"\$Net00002_.FBK".LFBK
"&__A__8".PRLD = GND
"&__A__9".T = "\$Net00002_" * "&__A__12.FBK".LFBK *
"&__A__10.FBK".LFBK * "&__A__11.FBK".LFBK
+ "\$Net00002_" * "&__A__12.FBK".LFBK *
/"&__A__10.FBK".LFBK * "&__A__9.FBK".LFBK * /"&__A__11.FBK".LFBK
"&__A__9".CLKF = "\$Net00006_.FBK".LFBK
"&__A__9".RSTF = /CLK * /"\$Net00002_"
"&__A__9".PRLD = GND
"\$Net00009_" := "&__A__16.FBK".LFBK
"\$Net00009_".CLKF = /"\$Net00002_"
"\$Net00009_".PRLD = GND
"\$Net00046_" := "&__A__15.FBK".LFBK
"\$Net00046_".CLKF = /"\$Net00002_"
"\$Net00046_".PRLD = GND
"\$Net00047_" := "&__A__14.FBK".LFBK
"\$Net00047_".CLKF = /"\$Net00002_"
"\$Net00047_".PRLD = GND
"\$Net00042_" := "&__A__13.FBK".LFBK
"\$Net00042_".CLKF = /"\$Net00002_"
"\$Net00042_".PRLD = GND
"\$Net00044_" := "&__A__12"
"\$Net00044_".CLKF = /"\$Net00002_"
"\$Net00044_".PRLD = GND
"\$Net00041_" := "&__A__11.FBK".LFBK
"\$Net00041_".CLKF = /"\$Net00002_"
"\$Net00041_".PRLD = GND
"\$Net00043_" := "&__A__10"
"\$Net00043_".CLKF = /"\$Net00002_"
"\$Net00043_".PRLD = GND
"\$Net00045_" := "&__A__9"
"\$Net00045_".CLKF = /"\$Net00002_"
"\$Net00045_".PRLD = GND
"\$Net00050_" := "&__A__8"
"\$Net00050_".CLKF = /"\$Net00002_"
"\$Net00050_".PRLD = GND
"\$Net00048_" := "&__A__7.FBK".LFBK
"\$Net00048_".CLKF = /"\$Net00002_"
"\$Net00048_".PRLD = GND
"\$Net00049_" := "&__A__6"
"\$Net00049_".CLKF = /"\$Net00002_"
"\$Net00049_".PRLD = GND
"\$Net00051_" := "&__A__5.FBK".LFBK
"\$Net00051_".CLKF = /"\$Net00002_"
"\$Net00051_".PRLD = GND
"\$Net00039_" := "&__A__4"
"\$Net00039_".CLKF = /"\$Net00002_"
"\$Net00039_".PRLD = GND
"\$Net00037_" := "&__A__3.FBK".LFBK
"\$Net00037_".CLKF = /"\$Net00002_"
"\$Net00037_".PRLD = GND
"\$Net00038_" := "&__A__2"
"\$Net00038_".CLKF = /"\$Net00002_"
"\$Net00038_".PRLD = GND
"\$Net00040_" := "&__A__1.FBK".LFBK
"\$Net00040_".CLKF = /"\$Net00002_"
"\$Net00040_".PRLD = GND
"\$Net00002_" := /"\$Net00002_.FBK".LFBK
"\$Net00002_".CLKF = CLK
"\$Net00002_".PRLD = GND
"\$Net00004_" := /"\$Net00002_" * "\$Net00004_.FBK".LFBK
+ "&__A__8" * /"&__A__6" * "\$Net00002_" *
/"&__A__7.FBK".LFBK * "&__A__5.FBK".LFBK
"\$Net00004_".CLKF = "\$Net00005_"
"\$Net00004_".RSTF = /CLK * /"\$Net00002_"
"\$Net00004_".PRLD = GND
"\$Net00005_" := /"\$Net00002_" * "\$Net00005_.FBK".LFBK
+ "\$Net00002_" * "&__A__12.FBK".LFBK *
/"&__A__10.FBK".LFBK * "&__A__9.FBK".LFBK * /"&__A__11.FBK".LFBK
"\$Net00005_".CLKF = "\$Net00006_.FBK".LFBK
"\$Net00005_".RSTF = /CLK * /"\$Net00002_"
"\$Net00005_".PRLD = GND
"\$Net00006_" := /"\$Net00002_" * "\$Net00006_.FBK".LFBK
+ "\$Net00002_" * "&__A__16.FBK".LFBK *
/"&__A__15.FBK".LFBK * /"&__A__14.FBK".LFBK * "&__A__13.FBK".LFBK
"\$Net00006_".CLKF = UCLK
"\$Net00006_".RSTF = /CLK * /"\$Net00002_"
"\$Net00006_".PRLD = GND
**************************** Device Pin Out ****************************
Device : XC9572-10-PC84
T T T G T T T T T T T T T T T T T V T T T
I I I N I I I I I I I I I I I I I C I I I
E E E D E E E E E E E E E E E E E C E E E
--------------------------------------------------------------
/11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 \
TIE | 12 74 | TIE
TIE | 13 73 | VCC
TIE | 14 72 | TIE
TIE | 15 71 | TIE
GND | 16 70 | TIE
TIE | 17 69 | TIE
TIE | 18 68 | TIE
TIE | 19 67 | TIE
TIE | 20 66 | TIE
TIE | 21 XC9572-10-PC84 65 | TIE
VCC | 22 64 | VCC
TIE | 23 63 | TIE
TIE | 24 62 | TIE
TIE | 25 61 | TIE
TIE | 26 60 | GND
GND | 27 59 | TDO
TDI | 28 58 | \$Net00048_
TMS | 29 57 | \$Net00050_
TCK | 30 56 | TIE
UCLK | 31 55 | \$Net00040_
CLK | 32 54 | \$Net00038_
\ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
--------------------------------------------------------------
\ T T T T V T \ \ G \ \ \ \ \ T G \ \ \ \
$ I I I I C I $ $ N $ $ $ $ $ I N $ $ $ $
N E E E E C E N N D N N N N N E D N N N N
e e e e e e e e e e e e
t t t t t t t t t t t t
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
4 0 4 4 4 4 4 4 4 5 3 3
7 9 6 2 4 1 3 5 9 1 9 7
_ _ _ _ _ _ _ _ _ _ _ _
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9572-10-PC84
Use Timing Constraints : ON
Use Design Location Constraints : ON
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : ON
Use Pin Feedback : ON
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : ON
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 36
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